MT46H32M32LFCM-6 IT:A Micron Technology Inc, MT46H32M32LFCM-6 IT:A Datasheet
MT46H32M32LFCM-6 IT:A
Specifications of MT46H32M32LFCM-6 IT:A
Related parts for MT46H32M32LFCM-6 IT:A
MT46H32M32LFCM-6 IT:A Summary of contents
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... PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN Products and specifications discussed herein are subject to change by Micron without notice. 1Gb: x16, x32 Mobile LPDDR SDRAM Options • DDQ – 1.8V/1.8V • Configuration – 64 Meg x 16 (16 Meg banks) – 32 Meg Meg banks) • ...
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... Micron’s FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/ Meg (A[12:0]) 1K (A[9:0]) H 64M16 1Gb: x16, x32 Mobile LPDDR SDRAM Reduced Page-Size Option 32 Meg Meg banks 8K 16K (A[13:0]) 512 (A[8:0 Design Revision :A = First generation Operating Temperature Blank = Commercial (0° ...
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... Rev. L – 04/10 ............................................................................................................................................. 93 Rev. K – 07/09 ............................................................................................................................................. 93 Rev. J – 06/09 .............................................................................................................................................. 93 Rev. I – 03/09 .............................................................................................................................................. 93 PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...
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... Update – 05/08 ........................................................................................................................................... 95 Update – 03/08 ........................................................................................................................................... 95 Update – 12/07 ........................................................................................................................................... 95 Update – 07/07 ........................................................................................................................................... 95 PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...
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... Table 17: Truth Table – Current State Bank n – Command to Bank m .............................................................. 40 Table 18: Truth Table – CKE .......................................................................................................................... 43 Table 19: Burst Definition Table .................................................................................................................... 49 PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...
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... Figure 46: Bank Write – With Auto Precharge .................................................................................................. 84 Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 85 Figure 48: Auto Refresh Mode ........................................................................................................................ 86 Figure 49: Self Refresh Mode ......................................................................................................................... 88 Figure 50: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 89 PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t t DQSQ, QH, and Data Valid Window (x16) ................................................... DQSQ, QH, and Data Valid Window (x32) ...
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... Figure 51: Power-Down Mode (Active or Precharge) ....................................................................................... 90 Figure 52: Deep Power-Down Mode .............................................................................................................. 91 Figure 53: Clock Stop Mode ........................................................................................................................... 92 PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...
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... The 1Gb Mobile low-power DDR SDRAM is a high-speed CMOS, dynamic random-ac- cess memory containing 1,073,741,824 bits internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1,024 col- umns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8,192 rows by 1,024 columns by 32 bits. In the reduced page-size (LG) option, each of the x32’ ...
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... Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column decoder Column- address counter/ latch 1 9 1Gb: x16, x32 Mobile LPDDR SDRAM Functional Block Diagrams Bank 3 Data Read MUX latch 16 2 DQS generator COL 0 Input CK 32 registers ...
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... Sense amplifiers I/O gating 2 DM mask logic Bank control logic 2 Column decoder Column- address counter/ latch 1 10 1Gb: x16, x32 Mobile LPDDR SDRAM Functional Block Diagrams Bank 3 Data Read MUX latch 32 2 DQS generator COL 0 Input CK 64 registers ...
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... Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA – 10mm x 11.5mm (Top View Note test pin that must be tied to V PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM DQ15 V SS SSQ V DQ13 DQ14 DDQ V DQ11 DQ12 SSQ V DQ9 DQ10 ...
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... Figure 5: 90-Ball VFBGA – 10mm x 13mm (Top View test pin that must be tied to V Note: PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM DQ31 V SS SSQ V DQ29 DQ30 DDQ V DQ27 DQ28 SSQ V DQ25 DQ26 DDQ V DQS3 DQ24 SSQ ...
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... Data strobe: Output with read data, input with write data. DQS is output edge-aligned with read data, center-aligned in write data used to capture data. 13 1Gb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...
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... Input Do not use. A13 if reduced page-size option is selected; otherwise, DNU. TEST Input Test pin: Must be tied 1Gb: x16, x32 Mobile LPDDR SDRAM Ball Assignments and Descriptions normal operations. SS SSQ Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. ...
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... The pre-reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.6 7.2 0.8 TYP 0.8 TYP 1. All dimensions are in millimeters. Note: PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 0.65 ±0.05 10 ±0.1 5 ±0.05 Ball 5.75 ±0. 11.5 ±0.1 ...
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... 0.8 TYP 6.4 16 1Gb: x16, x32 Mobile LPDDR SDRAM Package Dimensions Solder ball material: SAC105 (98.5% Sn, 1% Ag, 0.5% Cu) Substrate material: plastic laminate Mold compound: epoxy novolac Ball A1 ID 1.0 MAX Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... 0.7 × V IH(DC) V IL(DC) V 0.8 × V IH(AC) V IL(AC) = –0.1mA) V 0.9 × 0.1mA 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max –1.0 2.4 –0.5 2 DDQ whichever is less –55 +150 DDQ Min Max Unit 1.70 1.95 1.70 1. 0.3 DDQ DDQ – ...
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... V IX variations in the DC level of the same added to DS and DH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. Symbol 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max – +70 –40 +85 50 I/O 10pF Half drive strength -to-V swing ...
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... V (peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the DDQ OUT fact that they are matched in loading. for any given device. mum amount for any given device. 19 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications Min Max Unit – 0. ...
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... Data bus inputs are stable Typical deep power-down current at 25°C: Address and control balls are stable; Data bus inputs are stable PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I Parameters 1.70–1.95V ...
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... Data bus inputs are stable Typical deep power-down current at 25°C: Address and control pins are stable; Data bus inputs are stable PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – 1.70–1.95V DD DDQ ...
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... RFC later. t command period ( RFC [MIN]) else CKE is LOW (for example, during standby). 85˚C are guaranteed for the entire temperature range. All other I DD6 ues are estimated. 22 1Gb: x16, x32 Mobile LPDDR SDRAM /V = 1.70–1.95V DD DDQ Symbol Low Power Standard I ...
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... PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Electrical Specifications – I – Temperature (°C) 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... DSH 0.2 0.2 t – DSS 0 DQSQ QH - DQSQ – HP CH, CH 1Gb: x16, x32 Mobile LPDDR SDRAM -6 -75 Max Min Max Min Max 5.0 2.0 5.5 2.0 6.0 6.5 2.0 6.5 2.0 6.5 – – – 6 7.5 – – – 0.55 ...
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... RRD 10 10.8 t – SRC – SRR – WPRE 0.25 0.25 25 1Gb: x16, x32 Mobile LPDDR SDRAM -6 -75 Max Min Max Min Max – – 5.0 5.5 6.0 – – 6.5 6.5 6.5 – – – 1.0 1.0 – ...
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... IH timing is still referenced the crossing point for CK/CK#. The output tim- DDQ ing reference voltage level is V DDQ mode. of the clock and ends when CKE transitions HIGH. 26 1Gb: x16, x32 Mobile LPDDR SDRAM -6 -75 Max Min Max Min Max – – ...
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... If a previous WRITE was in progress, DQS could be HIGH t during this time, depending on DQSS. a greater value for this parameter, but system performance (bus turnaround) will de- grade accordingly. 27 1Gb: x16, x32 Mobile LPDDR SDRAM to V for rising input signals and V IH(AC ...
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... I-V curves. 28 1Gb: x16, x32 Mobile LPDDR SDRAM Output Drive Characteristics Pull-Up Current (mA) Min 0.00 –2.80 –5.60 –8.40 –11.20 –14.00 –16.80 –19.60 – ...
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... I-V curves. 29 1Gb: x16, x32 Mobile LPDDR SDRAM Output Drive Characteristics Pull-Up Current (mA) Min 0.00 –1.96 –3.92 –5.88 –7.84 –9.80 –11.76 –13.72 – ...
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... I-V curves. strength. 30 1Gb: x16, x32 Mobile LPDDR SDRAM Output Drive Characteristics Pull-Up Current (mA) Min 0.00 –1.27 –2.55 –3.82 –5.09 –6.36 –7.64 –8.91 – ...
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... Functional Description The Mobile LPDDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O. Single read or write access for the device consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock- cycle data transfers at the I/O ...
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... READ bursts with auto precharge enabled and for WRITE bursts. LOW. A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.” are “Don’t Care” except for CKE. 32 1Gb: x16, x32 Mobile LPDDR SDRAM RAS# CAS# WE# Address ...
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... A[0:n] selects the row. This row remains active for accesses until a PRE- CHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Valid ...
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... PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN CK# CK CKE HIGH CS# WE# Row Bank Don’t Care 34 1Gb: x16, x32 Mobile LPDDR SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. Commands ...
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... CK# CK CKE HIGH CS# RAS# WE# Column EN AP A10 DIS AP Bank Don’t Care 35 1Gb: x16, x32 Mobile LPDDR SDRAM WTR are satisfied. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. Commands ...
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... A10 DIS AP Bank Don’t Care t RP) after the PRECHARGE command is issued. Input A10 determines 36 1Gb: x16, x32 Mobile LPDDR SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. Commands ...
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... AUTO REFRESH AUTO REFRESH is used during normal operation of the device and is analogous to CAS#- BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is required. Addressing is generated by the internal refresh controller. This makes the address bits a “ ...
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... CAS# Address BA0, BA1 PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN CK# CK CKE CS# WE# Don’t Care 38 1Gb: x16, x32 Mobile LPDDR SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2007 Micron Technology, Inc. All rights reserved. Commands ...
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... RP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when t met. After RCD is met, the bank will be in the row active state. 39 1Gb: x16, x32 Mobile LPDDR SDRAM t is HIGH and after XSR has been met ( ...
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... L H READ (select column and start READ burst WRITE (select column and start new WRITE burst PRECHARGE 40 1Gb: x16, x32 Mobile LPDDR SDRAM has been met. After RP is met, the bank will has been met. After RP is met, the bank t MRD is met, the device will be in the all Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
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... To Command WRITE with READ or READ with auto precharge Auto Precharge WRITE or WRITE with auto precharge PRECHARGE ACTIVE 41 1Gb: x16, x32 Mobile LPDDR SDRAM t is HIGH and after XSR has been met ( has been met (if the previous state was power has been met. ...
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... PRECHARGE ACTIVE banks are idle. BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com- mand. 42 1Gb: x16, x32 Mobile LPDDR SDRAM Minimum Delay (with Concurrent Auto Precharge) (BL/2) × [CL + (BL/2)] Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... CKE Notes: 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMAND 4. All states and sequences not shown are illegal or reserved. 5. DESELECT or NOP commands should be issued on each clock edge occurring during the 6. After exiting deep power-down mode, a full DRAM initialization sequence is required. ...
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... WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD = Enter deep power-down PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Self refresh DPDX Deep SREFX power- down SREF DPD SRR ...
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... Typically, both of these commands are issued at this stage as de- scribed above. desired. the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical. 45 1Gb: x16, x32 Mobile LPDDR SDRAM ) must be brought up simultaneously. DDQ be from the same power source DDQ t ...
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... High High RFC FRESH command; ACT = ACTIVE command. 46 1Gb: x16, x32 Mobile LPDDR SDRAM Tb0 Tc0 Td0 ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ) ...
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... NOP PRE FRESH command; ACT = ACTIVE command. 47 1Gb: x16, x32 Mobile LPDDR SDRAM Tb0 Tc0 Td0 ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ) ( ( ( ( ( ( ) ) ) ) ) ...
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... M10 Operating Mode Normal operation – – – – – All other states reserved 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register t MRD before initiating the subse Address bus Standard mode register (Mx) CAS Latency BT Burst Length Burst Length Reserved ...
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... 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A D-E-F-0-1-2-3-4-5-6-7-8-9-A-B E-F-0-1-2-3-4-5-6-7-8-9-A-B-C F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E t AC). For the READ command is regis- 50 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/ T1n CK# CK READ NOP DQS CK# CK READ NOP DQS DQ 51 1Gb: x16, x32 Mobile LPDDR SDRAM Standard Mode Register T2 T2n T3 T3n NOP NOP OUT OUT OUT OUT T2n T3 T3n NOP NOP t AC ...
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... Operation E7–E0 Normal AR operation Valid – All other states reserved 52 1Gb: x16, x32 Mobile LPDDR SDRAM Extended Mode Register Address bus Extended mode 1 TCSR PASR register (Ex Partial-Array Self Refresh Coverage Full array 1/2 array 1/4 array Reserved Reserved 1/8 array ...
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... The output driver settings are 25Ω, 37Ω, and 55Ω internal impedance for full, three-quarter, and one-half drive strengths, respectively. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM Extended Mode Register 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... T4 t SRR 2 LMR NOP READ 0 BA0 = 1 BA1 = SRR), and between the READ and the next VALID command ( as an example only. 54 1Gb: x16, x32 Mobile LPDDR SDRAM Status Read Register t SRC after the SRR READ com SRC NOP NOP NOP SRR out Don’ ...
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... IBIS (pull pull-down characteristics), or process occurs quired average periodic refresh interval = 55 1Gb: x16, x32 Mobile LPDDR SDRAM Status Read Register I/O bus (CLK L->H edge) DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 ...
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... The mini- mum time interval between successive ACTIVE commands to different banks is defined t by RRD. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t RCD specification. 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. Bank/Row Activation t RC. © ...
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... READ command, where x equals the number of desired data element pairs. This is shown in Figure 28 (page 64). Following the PRECHARGE command, a subsequent PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t DQSQ (valid data-out skew), t DQSCK (DQS transition skew to CK) and 57 Micron Technology, Inc ...
Page 58
... T1 T1n T2 T2n NOP NOP OUT OUT T1 T2 T2n NOP NOP data-out from column n. OUT t t AC, DQSCK, and 58 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation met. Part of the row precharge T3 T3n T4 NOP NOP OUT OUT T3 T3n T4 NOP NOP OUT OUT OUT OUT Don’ ...
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... NOP READ Bank, Col OUT OUT T2n NOP READ Bank, Col ( data-out from column n (or column b). OUT the first AC, DQSCK, and 59 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n T4 T4n T5 NOP NOP NOP OUT OUT OUT OUT OUT T3n T4 T4n ...
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... OUT T1n T2 T2n T3 NOP NOP READ Bank, Col OUT data-out from column n (or column b). OUT t t AC, DQSCK, and tive READs. 60 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3n T4 T4n T5 T5n NOP NOP OUT OUT T3n T4 T4n T5 T5n NOP NOP ...
Page 61
... READ Bank, Address Col n DQS Notes ( 16, the following burst interrupts the previous). 3. READs are to an active row in any bank. 4. Shown with nominal PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n READ READ Bank, Bank, Col x Col ...
Page 62
... DQ T0 CK# CK Command 1 READ Bank a, Address Col n DQS 16. Notes: 2. BST = BURST TERMINATE command; page remains open Shown with nominal 5. CKE = HIGH. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 2 BST NOP OUT OUT T2n 2 BST NOP ...
Page 63
... BST NOP OUT OUT T2n 2 BST NOP mand shown can be NOP data-out from column n. OUT b = data-in from column AC, DQSCK, and 63 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n T4 T4n T5 1 WRITE NOP NOP Bank, Col b t DQSS (NOM b+1 b+2 T3 ...
Page 64
... PRE Bank all data-out from column n. OUT t t AC, DQSCK, and cause a precharge to be performed at x number of clock cycles after the READ com- mand, where x = BL/2. 64 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n T4 T5 NOP NOP ACT Bank a, Row t RP ...
Page 65
... DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. er byte and UDQS defines the upper byte derived from HP 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n ...
Page 66
... DQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with DQS transition and ends with the last valid DQ transition derived from HP byte 2; DQ[31:23] and DQS3 for byte 3. 66 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3 T3n 2,3 ...
Page 67
... NOP NOP DQSCK RPRE T2n DQSQ after DQS transitions, regardless the DQ output window relative to CK and is the long-term component of DQ skew. 67 1Gb: x16, x32 Mobile LPDDR SDRAM READ Operation T3n T4 T4n T5 T5n 1 1 NOP NOP t DQSCK T4 T3 T3n T4n DQSQ window. ...
Page 68
... Data for any WRITE burst can be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, Figure 41 (page 77). PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM DQSS [MAX]) might not be obvious, they have also been included. Figure 34 68 Micron Technology, Inc ...
Page 69
... DSH (MIN) generally occurs during t DSS (MIN) generally occurs during trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls DQ[31:24]. trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls DQ[31:24]. 69 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation met. T2 T2n T3 3 ...
Page 70
... IS IH Note 4 Bank DQSS (NOM) RCD t RAS t t WPRE WPRES these times data-in from column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4n T5 T5n NOP NOP NOP DQSL DQSH WPST Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 71
... DQSS DQS b DQSS DQS b DQSS DQS Don’t Care b = data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T2 T2n T3 NOP NOP b+2 b b+2 b b+1 b+2 b+3 Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 72
... CK# CK Command 1, 2 WRITE Bank, Address Col b t DQSS (NOM) DQS Each WRITE command can be to any bank. Notes uninterrupted burst shown PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 T1n T2 T2n 1, 2 NOP WRITE Bank, Col b+1 ...
Page 73
... Rev. L 04/ T1n T2 T2n 1,2 1,2 WRITE WRITE Bank, Bank, Col x Col b’ x x’ data-in for column b ( g). IN med burst order. 73 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T3 T3n T4 T4n T5 1,2 1,2 WRITE WRITE NOP Bank, Bank, Col a Col n’ a a’ ...
Page 74
... READ command could be applied earlier. t WTR is referenced from the first positive CK edge after the last data-in pair data-in for column data-out for column n. IN OUT 74 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T5n T4 T5 READ NOP 4 Bank a, ...
Page 75
... b+1 t WTR is referenced from the first positive CK edge after the last data-in pair data-in for column data-out for column n. IN OUT 75 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4 T5 T5n NOP NOP Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 76
... WTR is referenced from the first positive CK edge after the last data-in pair data-in for column data-out for column n. IN OUT 76 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4 T5 T5n NOP NOP Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 77
... CHARGE and WRITE commands can be to different devices; in this case, required and the PRECHARGE command can be applied earlier referenced from the first positive CK edge after the last data-in pair data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T4 T5 3,4 NOP PRE ...
Page 78
... referenced from the first positive CK edge after the last data-in pair data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T3n T4 T4n T5 3 PRE NOP Bank (a or all) Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 79
... T2n T3 NOP NOP NOP referenced from the first positive CK edge after the last data-in pair data-in for column 1Gb: x16, x32 Mobile LPDDR SDRAM WRITE Operation T3n T4 T4n T5 3 NOP PRE Bank (a or all) Don’t Care Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 80
... Figure 45 (page 83). Bank WRITE operations with and without auto precharge are shown in Figure 46 (page 84) and Figure 47 (page 85). PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t RP) after the PRECHARGE command is issued. Input A10 deter (the precharge period) begins. For READ with auto pre- ...
Page 81
... PRECHARGE command, thus freeing the command bus for operations in other banks. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. Auto Precharge © 2007 Micron Technology, Inc. All rights reserved. ...
Page 82
... NOP READ NOP Col n Note Bank x t RCD t RAS RPRE t AC (MIN (MIN (MIN) these times data-out from column n. OUT 82 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T5 T5n T6 T6n NOP NOP DQSCK (MIN) t RPST OUT OUT OUT OUT RPRE DQSCK (MAX) ...
Page 83
... RCD 6 t RAS RPRE t AC (MIN (MIN) D OUT (MIN) t RPRE t AC (MAX) these times data out from column n. OUT 83 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T5 T5n T6 T6n PRE NOP NOP All banks One bank 5 Bank DQSCK (MIN) t RPST OUT ...
Page 84
... IH IS Bank DQSS (NOM) RCD t RAS t t WPRE WPRES these times data-out from column 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T4n T5 T5n NOP NOP NOP DQSL DQSH WPST t DH Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 85
... RCD t RAS t DQSS (NOM WPRES WPRE these times data-out from column n. OUT 85 1Gb: x16, x32 Mobile LPDDR SDRAM Auto Precharge T4n T5 T5n NOP NOP NOP DQSL DQSH WPST Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 86
... AUTO REFRESH Operation Auto refresh mode is used during normal operation of the device and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAM. The AUTO REFRESH com- mand is nonpersistent and must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “ ...
Page 87
... SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t XSR to complete any internal refresh already in progress. 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 88
... Care.” The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). NOP or DESELECT commands must be maintained on the command bus until satisfied. See Figure 51 (page 90) for a detailed illustration of power-down mode. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM T1 Ta0 ( ( ) ...
Page 89
... Figure 50: Power-Down Entry (in Active or Precharge Mode) RAS#, CAS#, WE# RAS#, CAS#, WE# PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM CK# CK CKE CS# Or CS# Address BA0, BA1 Don’t Care 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 90
... LOW to maintain DPD mode. The clock must be stable prior to exiting DPD mode. To exit DPD mode, assert CKE HIGH with either a NOP or DESELECT com- mand present on the command bus. After exiting DPD mode, a full DRAM initialization sequence is required. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m ...
Page 91
... All banks idle with no activity on the data bus 1. Clock must be stable prior to CKE going HIGH. Notes: 2. DPD = deep power-down. 3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required. PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 1 T1 ...
Page 92
... The device enables the clock to change frequency during operation only if all timing parameters are met and all refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that would be affected by this change. Any DRAM operation already in process must be com- pleted before entering clock stop mode ...
Page 93
... Added burst length of 16 and note reference to “Features” • Updated values in Table 6, “Capacitance (x16, x32)” PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM t RC min value for -75 from 75ns to 67.5ns in Table 10 (page 24). description for Table 7 (page 20) and Table 8 (page 21). ...
Page 94
... Figure 1: “512Mb Mobile DDR Part Numbering,” and Figure 8: “90-Ball VFBGA Package (9mm x 13mm)” PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. Revision History ...
Page 95
... Corrected headings for density in Figure 21: “Status Register Definition” Update – 07/07 • Initial Release PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. Revision History © 2007 Micron Technology, Inc. All rights reserved. ...
Page 96
... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef82ce3074 1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN 1Gb: x16, x32 Mobile LPDDR SDRAM times occur. 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...