K4T1G164QE-HCE6000 Samsung Semiconductor, K4T1G164QE-HCE6000 Datasheet - Page 10

• Manufacturer Part Number: K4T1G164QE-HCE6000
• Manufacturer: Samsung Semiconductor
• Type: DDR2 SDRAMr

Specifications of K4T1G164QE-HCE6000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

4.0 Input/Output Functional Description
K4T1G084QE
K4T1G164QE
K4T1G044QE
(UDQS), (UDQS)
(RDQS), (RDQS)
(LDQS), (LDQS)
RAS, CAS, WE
DQS, (DQS)
V
V
BA0 - BA2
A0 - A13
DD
Symbol
SS
CK, CK
V
V
V
CKE
ODT
DM
DQ
NC
SSDL
CS
/ V
/ V
DDL
REF
DDQ
SSQ
Input/Out-
Input/Out-
Supply
Supply
Supply
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
put
put
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out-
put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active
Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry.
CKE is asynchronous for self refresh exit. After V
sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, V
must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during
self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-
tems with multiple Ranks. CS is considered part of the command code.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16
configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be
ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only,
the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by
EMRS command.
Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines if the mode register or extended mode register is to be accessed during
a MRS or EMRS cycle.
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for
Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a
Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur-
ing Mode Register Set commands.
Data Input/ Output: Bi-directional data bus.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the
x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS
option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS,
and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and
RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables
or disables all complementary data strobe signals.
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1)
"single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1)
No Connect: No internal electrical connection is present.
Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V
Ground, DQ Ground
DLL Power Supply: 1.8V +/- 0.1V
DLL Ground
Reference voltage
x4 DQS
x8 DQS if EMRS(1)[A11] = 0
x8 DQS, RDQS, if EMRS(1)[A11] = 1
x16 LDQS and UDQS
x4 DQS/DQS
x8 DQS/DQS
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
if EMRS(1)[A11] = 0
10 of 45
if EMRS(1)[A11] = 1
REF
Function
has become stable during the power on and initialization
Rev. 1.1 December 2008
DDR2 SDRAM
REF