MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 105

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Write Leveling Procedure
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a “1,”
assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and
the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from
a High-Z state to an undefined driving state, so the DQ bus should not be driven. During
write leveling mode, only the NOP or DES commands are allowed. The memory
controller should attempt to level only one rank at a time; thus, the outputs of other
ranks should be disabled by setting MR1[12] to a “1” in the other ranks. The memory
controller may assert ODT after a
ODT transition. ODT should be turned on prior to DQS being driven LOW by at least
ODTL on delay (WL - 2
delay requirement.
The memory controller may drive DQS LOW and DQS# HIGH after
satisfied. The controller may begin to toggle DQS after
transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH
state to a LOW state, then both transition back to their original states). At a minimum,
ODTL on and
After
controller may provide either a single DQS toggle or multiple DQS toggles to sample CK
for a given DQS-to-CK skew. Each DQS toggle must not violate
t
applicable during write leveling mode. The DQS must be able to distinguish the CK’s
rising edge within
asynchronously from the associated DQS rising edge CK capture within
remaining DQ that always drive LOW when DQS is toggling must be LOW within
after the first
an input and not an output during this process. Figure 46 on page 106 depicts the basic
timing parameters for the overall write leveling procedure.
The memory controller will likely sample each applicable prime DQ state and determine
whether to increment or decrement its DQS delay setting. After the memory controller
performs enough DQS toggles to detect the CK’s “0-to-1” transition, the memory
controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting, leveling for the rank will have been achieved, and the write leveling mode for the
rank should be disabled or reprogrammed (if write leveling of another rank follows).
DQSH (MIN) specifications.
t
WLMRD and a DQS LOW preamble (
t
WLO is satisfied (the prime DQ going LOW). As previously noted, DQS is
t
AON must be satisfied at least one clock prior to DQS toggling.
t
WLS and
t
CK), provided it does not violate the aforementioned
t
105
t
WLH. The prime DQ will output the CK’s status
DQSL (MAX) and
t
MOD delay as the DRAM will be ready to process the
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WPRE) have been satisfied, the memory
t
DQSH (MAX) specifications are not
2Gb: x4, x8, x16 DDR3 SDRAM
t
WLMRD (one DQS toggle is DQS
©2006 Micron Technology, Inc. All rights reserved.
t
DQSL (MIN) and
t
WLDQSEN has been
t
WLO. The
Commands
t
MOD
t
WLOE