MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 130

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MT41J256M8HX-15E:D

Manufacturer Part Number
MT41J256M8HX-15E:D
Description
MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-15E:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
165mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Compliant

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Figure 64: Example: Meeting
Figure 65: Example:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Command
Command
Address
BA[2:0]
Address
BA[2:0]
CK#
CK#
CK
CK
Bank x
Bank a
Row
ACT
Row
T0
ACT
T0
NOP
t RRD
NOP
T1
T1
t
FAW
the next whole number to determine the earliest clock edge after the ACTIVATE
command on which a READ or WRITE command can be entered. The same procedure is
used to convert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-to-
WRITE command delay is restricted to
A subsequent ACTIVATE command to a different row in the same bank can only be
issued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVATE commands to different banks is defined by
t
t
eter applies, regardless of the number of banks already opened or closed.
RRD. No more than four bank ACTIVATE commands may be issued in a given
FAW (MIN) period, and the
t RRD
Bank b
NOP
Row
ACT
T2
T4
t
RRD (MIN) and
Bank y
Row
ACT
NOP
T3
T5
t
Bank c
RCD (MIN)
NOP
ACT
Row
T4
T8
t
RRD (MIN) restriction still applies. The
130
t FAW
NOP
NOP
T9
T5
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CCD (MIN).
t RCD
Bank d
Row
ACT
NOP
T10
T8
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
T11
NOP
Indicates a Break in
Time Scale
T9
Indicates a Break in
Time Scale
©2006 Micron Technology, Inc. All rights reserved.
t
NOP
T19
FAW (MIN) param-
NOP
T10
Operations
Bank y
Bank y
Bank e
RD/WR
Bank y
T20
Row
ACT
Don’t Care
T11
Don’t Care
Col
t
RC.

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