MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 131

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

READ
Figure 66: READ Latency
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
DQS, DQS#
Command
Address
CK#
DQ
CK
Bank a,
READ
Col n
T0
Notes:
CL = 8, AL = 0
READ bursts are initiated with a READ command. The starting column and bank
addresses are provided with the READ command and auto precharge is either enabled
or disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of POSTED CAS ADDI-
TIVE latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is
programmable in the mode register via the MRS command. Each subsequent data-out
element will be valid nominally at the next positive or negative clock edge (that is, at the
next crossing of CK and CK#). Figure 66 shows an example of RL based on a CL setting of
8 and an AL setting of 0.
1. DO n = data-out from column n.
2. Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial low state on
DQS and HIGH state on DQS# is known as the READ preamble (
DQS and the HIGH state on DQS#, coincident with the last data-out element, is known
as the READ postamble (
commands have been initiated, the DQ will go High-Z. A detailed explanation of
(valid data-out skew),
depicted in Figure 77 on page 139. A detailed explanation of
skew to CK) is also depicted in Figure 77 on page 139.
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued
page 133. If BC4 is enabled,
output, as shown in Figure 68 on page 133. Nonconsecutive read data is reflected in
Figure 69 on page 134. DDR3 SDRAM do not allow interrupting or truncating any READ
burst.
NOP
T7
t
CCD cycles after the first READ command. This is shown for BL8 in Figure 67 on
NOP
T8
DO
n
t
QH (data-out window hold), and the valid data window are
t
RPST). Upon completion of a burst, assuming no other
NOP
T9
t
CCD must still be met which will cause a gap in the data
131
NOP
T10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Indicates a Break in
Time Scale
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
T11
Transitioning Data
t
DQSCK (DQS transition
©2006 Micron Technology, Inc. All rights reserved.
t
T12
NOP
RPRE). The low state on
Operations
NOP
T12
Don’t Care
t
DQSQ