MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 14

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Figure 5:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D2.fm - Rev G 2/09 EN
RZQ
V
SS
BA[2:0]
A[13:0]
Q
CK, CK#
ZQ
RESET#
RAS#
CAS#
ODT
WE#
CKE
A12
CS#
17
Address
register
128 Meg x 16 Functional Block Diagram
Mode registers
Control
logic
17
14
Refresh
counter
ZQCL, ZQCS
10
3
BC4 (burst chop)
OTF
13
address
3
Row-
MUX
Column-
counter/
address
control
14
Bank
latch
logic
ZQ CAL
decoder
address
Bank 0
row-
latch
and
Bank 1
Bank 2
7
3
Bank 3
Bank 4
16,384
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 7
(16,384 x 128 x 128)
To ODT/output drivers
Sense amplifiers
DM mask logic
I/O gating
decoder
memory
Column
Bank 0
16,384
x128)
(128
array
Bank 1
Bank 2
Bank 3
Bank 4
14
Bank 5
Bank 6
Bank 7
128
BC4
OTF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128
128
Column 0, 1, and 2
interface
CK, CK#
READ
Data
MUX
FIFO
data
and
2Gb: x4, x8, x16 DDR3 SDRAM
Data
16
lower nibble for BC4)
16
(select upper or
Functional Block Diagrams
Column 2
WRITE
drivers
input
logic
and
control
ODT
CK, CK#
drivers
READ
DLL
BC4
©2006 Micron Technology, Inc. All rights reserved.
DQ[15:0]
LDQS, LDQS#, UDQS, UDQS#
sw1
sw1
sw1
R
R
R
V
V
V
TT
TT
TT
DD
DD
DD
_
_
_
Q/2
NOM
Q/2
NOM
Q/2
NOM
R
R
R
sw2
TT
sw2
sw2
TT
TT
_
_
_
WR
WR
WR
(1 . . . 4)
(1, 2)
(1 . . . 16)
LDM/UDM
DQ[15:0]
LDQS, LDQS#
UDQS, UDQS#