MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 161

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

On-Die Termination (ODT)
Figure 107: On-Die Termination
Functional Representation of ODT
Nominal ODT
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D5.fm - Rev G 2/09 EN
ODT is a feature that enables the DRAM to enable/disable and turn on/off termination
resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and
TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ,
UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration.
The ODT feature is designed to improve signal integrity of the memory channel by
enabling the DRAM controller to independently turn on/off the DRAM’s internal termi-
nation resistance for any grouping of DRAM devices. The ODT feature is not supported
during DLL disable mode. A simple functional representation of the DRAM ODT feature
is shown in Figure 107. The switch is enabled by the internal ODT control logic, which
uses the external ODT ball and other control information.
The value of R
register bits (see Table 81 on page 164). The ODT ball is ignored while in self refresh
mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2
are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT
modes and either of these can function in synchronous or asynchronous mode (when
the DLL is off during precharge power-down or when the DLL is synchronizing).
Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic
ODT is applied only during writes and provides OTF switching from no R
to R
The actual effective termination, R
nonlinearity of the termination. For R
teristics” on page 52.
ODT (NOM) is the base termination resistance for each applicable ball, it is enabled or
disabled via MR1[9, 6, 2] (see Figure 53 on page 115), and it is turned on or off via the
ODT ball (see Table 78 on page 162).
To other
circuitry
such as
RCV,
. . .
TT
_
WR
.
ODT
TT
Switch
(ODT termination value) is determined by the settings of several mode
R
TT
V
DD
161
Q/2
TT
_
TT
EFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
_
EFF
, may be different from the R
DQ, DQS, DQS#,
DM, TDQS, TDQS#
values and calculations, see “ODT Charac-
2Gb: x4, x8, x16 DDR3 SDRAM
On-Die Termination (ODT)
©2006 Micron Technology, Inc. All rights reserved.
TT
targeted due to
TT
or R
TT
_
NOM