MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 169

no-image

MT41J256M8HX-15E:D

Manufacturer Part Number
MT41J256M8HX-15E:D
Description
MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-15E:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
165mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
SAMSUNG
Quantity:
1 001
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON
Quantity:
11 200
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON21
Quantity:
1 684
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT41J256M8HX-15E:D
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT41J256M8HX-15E:D
Quantity:
5 845
Part Number:
MT41J256M8HX-15E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 84:
Figure 113: Synchronous ODT
Symbol
ODTL on
ODTL off
ODTH4
ODTH8
t
t
AON
AOF
ODT
CKE
CK#
R
CK
TT
T0
Synchronous ODT Parameters
T1
ODT minimum HIGH time after ODT
Notes:
ODT turn-off relative to ODTL off
ODT turn-on relative to ODTL on
ODT synchronous turn-on delay
ODT synchronous turn-off delay
ODT minimum HIGH time after
assertion or WRITE (BC4)
T2
1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. R
AL = 3
Description
WRITE (BL8)
completion
completion
ODTH4 (MIN)
T3
ODTL on = CWL + AL - 2
T4
T5
Write registration with ODT
write registration with ODT
ODT registered HIGH, or
Completion of ODTL off
Completion of ODTL on
ODT registered HIGH
ODT registered HIGH
T6
Begins at
HIGH
HIGH
T7
t AON (MIN)
t AON (MAX)
T8
ODT registered LOW
ODT registered LOW
T9
AL = 3
R
R
Defined to
TT
TT
TT
_
_
R
_
R
ON
OFF
NOM
TT
TT
T10
_
_
ODTL off = CWL + AL - 2
±
OFF
±
ON
t
t
AON
is enabled.
AOF
R
TT
_
NOM
T11
Definition for All DDR3
See Table 56 on page 70
T12
CWL - 2
0.5
CWL + AL - 2
CWL + AL - 2
Speed Bins
t
CK ± 0.2
T13
6
4
t
t
Transitioning
CK
CK
t
CK
T14
t AOF (MIN)
t AOF (MAX)
Don’t Care
T15
Units
t
t
t
t
tCK
ps
CK
CK
CK
CK

Related parts for MT41J256M8HX-15E:D