MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 175

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D5.fm - Rev G 2/09 EN
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period occurs
if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins
and it ends when CKE is first registered LOW.
1
when CKE goes LOW, power-down entry will end
rather than when CKE is first registered LOW. Power-down entry will then become the
greater of
ODT assertion during power-down entry results in an R
t
(MAX) and ODTL on ×
may result in an R
off ×
off ×
If the AL has a large value, the uncertainty of the state of R
because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL.
Figure 117 on page 176 shows three different cases:
• ODT_A: Synchronous behavior before
• ODT_B: ODT state changes during the transition period with
• ODT_C: ODT state changes after the transition period with asynchronous behavior
AONPD (MIN) and ODTL on ×
t
CK or ODTL on + 1
ODTL on ×
ODTL on ×
t
t
CK +
CK +
t
ANPD and
t
t
AOF (MIN) or as late as the greater of
AOF (MAX). Table 86 on page 176 summarizes these parameters.
t
t
CK +
CK +
TT
t
t
t
AON (MIN) and
AON (MAX)
change as early as the lesser of
CK. If a REFRESH command has been issued, and it is in progress
t
RFC - REFRESH command to CKE registered LOW.
t
CK +
t
175
AON (MAX). ODT de-assertion during power-down entry
t
CK +
t
t
AONPD (MAX) greater than
AON (MIN) or as late as the greater of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
ANPD prior to CKE first being registered LOW,
t
ANPD
t
ANPD is equal to the greater of ODTL off +
t
2Gb: x4, x8, x16 DDR3 SDRAM
t
AOFPD (MAX) and ODTL
RFC after the REFRESH command
t
AOFPD (MIN) and ODTL
On-Die Termination (ODT)
TT
TT
change as early as the lesser of
becomes quite large. This is
©2006 Micron Technology, Inc. All rights reserved.
t
AONPD (MIN) less than
t
AONPD