MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 42

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MT41J256M8HX-15E:D

Manufacturer Part Number
MT41J256M8HX-15E:D
Description
MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-15E:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
165mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Compliant

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Electrical Specifications – DC and AC
DC Operating Conditions
Table 23:
Input Operating Conditions
Table 24:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D3.fm - Rev G 2/09 EN
Parameter/Condition
Parameter/Condition
Supply voltage
I/O supply voltage
Input leakage current
Any input 0V ≤ V
(All other pins not under test = 0V)
V
V
(All other pins not under test = 0V)
V
V
Input reference voltage command/address bus
I/O reference voltage DQ bus
I/O reference voltage DQ bus in SELF REFRESH
Command/address termination voltage
(system level, not direct DRAM input)
REF
REF
IN
IN
low; DC/commands/address busses
high; DC/commands/address busses
DQ = V
supply leakage current
DD
DC Electrical Characteristics and Operating Conditions
All voltages are referenced to V
DC Electrical Characteristics and Input Conditions
All voltages are referenced to V
/2 or V
IN
Notes:
Notes:
≤ V
REF
DD
CA = V
, V
REF
1. V
2. V
3. V
4. The minimum limit requirement is for testing purposes. The leakage current on the V
1. V
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifica-
3. V
4. V
5. V
DD
pin 0V ≤ V
(0Hz to 250 kHz) specifications. V
parameters.
should be minimal.
Externally generated peak noise (noncommon mode) on V
around the V
V
tions if the DRAM induces additional AC noise greater than 20 MHz in frequency.
level. Externally generated peak noise (noncommon mode) on V
× V
±2% of V
within restrictions outlined in the SELF REFRESH section.
tors. MIN and MAX values are system-dependent.
/2
DD
DD
REF
REF
REF
REF
REF
TT
DD
is not applied directly to the device. V
CA(
CA(
DQ(
DQ(
and V
and V
(see Table 24).
around the V
DC
DC
DC
DC
REF
IN
) is expected to be approximately 0.5 × V
).
DD
DD
) is expected to be approximately 0.5 × V
) may transition to V
DQ(
≤ 1.1V
Q must track one another. V
Q may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC
REF
SS
SS
CA(
DC
).
V
V
V
REF
DC
Symbol
REF
REF
REF
) value. Peak-to-peak AC noise on V
DQ(
V
V
V
Symbol
DQ(
CA(
DQ(
IH
TT
IL
V
I
V
VREF
DD
DC
DD
I
DC
DC
SR
I
42
) value. Peak-to-peak AC noise on V
Q
)
)
)
REF
DD
See Table 23
DQ(
0.49 × V
0.49 × V
and V
1.425
1.425
Min
Min
SR
V
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
–2
–1
SS
SS
) and back to V
Electrical Specifications – DC and AC
DD
TT
DD
DD
DD
Q must be less than or equal to V
is a system supply for signal termination resis-
Q must be at same level for valid AC timing
0.5 × V
0.5 × V
0.5 × V
0.5 × V
Nom
2Gb: x4, x8, x16 DDR3 SDRAM
1.5
1.5
DD
Nom
DD
n/a
n/a
and to track variations in the DC level.
and to track variations in the DC
DD
REF
DD
DD
DD
Q
REF
DQ(
REF
1.575
1.575
Max
CA should not exceed ±2% of
CA may not exceed ±1% × V
See Table 23
DC
0.51 × V
0.51 × V
2
1
REF
©2006 Micron Technology, Inc. All rights reserved.
) when in SELF REFRESH,
REF
Max
V
V
DQ may not exceed ±1%
DD
DD
DQ should not exceed
DD
DD
Units
µA
µA
V
V
Units
DD
V
V
V
V
V
V
. V
SS
Notes
1, 2
1, 2
3, 4
Notes
= V
REF
1, 2
2, 3
4
5
SS
pin
DD
Q.

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