MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 76

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Notes
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D3.fm - Rev G 2/09 EN
10. The clock’s
11. Spread spectrum is not included in the jitter specification values. However, the input
12. The clock’s
13. The period jitter (
14.
15.
16. The cycle-to-cycle jitter (
1. Parameters are applicable with 0°C
2. All voltages are referenced to V
3. Output timings are only valid for R
4. Unit “
5. AC timing and I
6. All timings that use time-based values (ns, µs, ms) should use
7. The use of “strobe” or “DQS
8. This output load is used for all AC timing (except ODT reference timing) and slew
9. When operating in DLL disable mode, Micron does not warrant compliance with nor-
Unit “CK” represents one clock cycle of the input clock, counting the actual clock
edges.
ronment, but input timing is still referenced to V
the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The
minimum slew rate for the input signals used to test the device is 1 V/ns for single-
ended inputs and 2 V/ns for differential inputs in the range between V
V
the correct number of clocks (Table 56 on page 70 uses “CK” or “
changeably). In the case of noninteger results, all minimum limits are to be rounded
up to the nearest whole integer, and all maximum limits are to be rounded down to
the nearest whole integer.
point when DQS is the rising edge. The use of “clock” or “CK” refers to the CK and CK#
differential crossing point when CK is the rising edge.
rates. The actual test load may be different. The output signal voltage reference point
is V
Figure 29 on page 63).
mal mode timings or functionality.
t
to clock jitter. Input clock jitter is allowed provided it does not exceed values specified
and must be of a random Gaussian distribution in nature.
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz
with an additional 1% of
spread-spectrum may not use a clock rate below
consecutive clocks and is the smallest clock half period allowed, with the exception of
a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed
values specified and must be of a random Gaussian distribution in nature.
age or nominal clock. It is allowed in either the positive or negative direction.
t
rising edge to the following falling edge.
t
falling edge to the following rising edge.
cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the
DLL locking time.
CK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due
CH(ABS) is the absolute instantaneous clock high pulse width as measured from one
CL(ABS) is the absolute instantaneous clock low pulse width as measured from one
IH
(
DD
AC
t
Q/2 for single-ended signals and the crossing point for differential signals (see
CK (AVG)” represents the actual
).
t
t
CK (AVG) is the average clock over any 200 consecutive clocks and
CH (AVG) and
DD
t
JIT
tests may use a V
PER
) is the maximum deviation in the clock period from the aver-
t
t
JIT
CK (AVG) as a long-term jitter component; however, the
t
76
CL (AVG) are the average half clock period over any 200
DIFF
CC
) is the amount the clock period can deviate from one
SS
” refers to the DQS and DQS# differential crossing
.
ON 34
≤
IL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T
-to-V
C
t
output buffer selection.
CK (AVG) of the input clock under operation.
≤
+95°C and V
IH
swing of up to 900mV in the test envi-
2Gb: x4, x8, x16 DDR3 SDRAM
REF
t
CK
(except
(AVG) MIN
DD
/V
DD
©2006 Micron Technology, Inc. All rights reserved.
t
IS,
t
Q = +1.5V ±0.075V.
CK (AVG) to determine
t
.
Speed Bin Tables
t
IH,
CK [AVG]” inter-
t
DS, and
IL
(
AC
) and
t
DH use