MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 78

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MT41J256M8HX-15E:D

Manufacturer Part Number
MT41J256M8HX-15E:D
Description
MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-15E:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
165mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Compliant

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PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D3.fm - Rev G 2/09 EN
34. The start of the write recovery time is defined as follows:
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
36. The refresh period is 64ms when T
37. Although CKE is allowed to be registered LOW after a REFRESH command when
38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins
39. Half-clock output parameters must be derated by the actual
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance.
41. Pulse width of a input signal is defined as the width between the first crossing of
42. Should the clock rate be larger than
– For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
– For BC4 (OTF): Rising clock edge four clock cycles after WL
– For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in
excessive current, depending on bus activity.
average refresh rate of 7.8125µs. However, nine REFRESH commands should be
asserted at least once every 70.3µs. When T
32ms.
t
t
to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The
ODT reference load is shown in Figure 21 on page 52.
when input clock jitter is present. This results in each parameter becoming larger. The
parameters
ing both
t
t
ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT refer-
ence load is shown in Figure 22 on page 54. This output load is used for ODT timings
(see Figure 29 on page 63).
V
should have at least one NOP command between it and another AUTO REFRESH
command. Additionally, if the clock rate is slower than 40ns (25 MHz) all REFRESH
commands should be followed by a PRECHARGE All command.
REFPDEN (MIN) is satisfied, there are cases where additional time such as
XPDLL (MIN) is required.
AOF (MAX) are required to be derated by subtracting both
JIT
REF
DTY
(
DC
(MAX).
) and the consecutive crossing of V
t
ERR
t
ADC (MIN) and
10PER
(MAX) and
78
t
AOF (MIN) are each required to be derated by subtract-
t
JIT
DTY
C
t
is less than or equal to 85
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RFC (MIN), an AUTO REFRESH command
(MAX). The parameters
REF
C
is greater than 85
(
2Gb: x4, x8, x16 DDR3 SDRAM
DC
).
t
©2006 Micron Technology, Inc. All rights reserved.
ERR
t
ERR
o
o
t
C. This equates to an
C, the refresh period is
ADC (MAX) and
Speed Bin Tables
10PER
10PER
(MAX) and
and
t
JIT
DTY

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