MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 94

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

Table 66:
DESELECT (DES)
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
Current State
Power-down
Self refresh
Bank(s) active
Reading
Writing
Precharging
Refreshing
All banks idle
Truth Table – CKE
Notes 1–2 apply to the entire table; see Table 65 on page 93 for additional command details
3
Previous Cycle
Notes:
(n - 1)
H
H
H
H
H
H
H
L
L
L
L
10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQ
4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four
5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 66 for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are
9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted
1. All states and sequences not shown are illegal or reserved unless explicitly described else-
2.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the pre-
5. COMMAND is the command registered at the clock edge (must be a legal command as
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings
The DES command (CS# HIGH) prevents new commands from being executed by the
DRAM. Operations already in progress are not affected.
mode registers.
defined in MR0.
commands. A NOP will not terminate an operation that is executing.
or ZQ
where in this document.
t
must remain at the valid input level the entire time it takes to achieve the required number
of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid
level during the time period of
vious clock edge.
defined in Table 65 on page 93). Action is a result of COMMAND. ODT does not affect the
states described in this table and is not listed.
from previous operations are satisfied. All self refresh exit and power-down exit parameters
are also satisfied.
CKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE
CKE
4
OPER
Present Cycle
(ZQCL command after initialization).
(n)
H
H
L
L
L
L
L
L
L
L
L
4
(RAS#, CAS#, WE#, CS#)
94
“Don’t Care”
“Don’t Care”
Command
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
DES or NOP
t
IS +
REFRESH
t
CKE (MIN) +
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
INIT
(first ZQCL command during initialization)
2Gb: x4, x8, x16 DDR3 SDRAM
t
IH.
Precharge power-down entry
Precharge power-down entry
Active power-down entry
Maintain power-down
Maintain self refresh
Power-down entry
Power-down entry
Power-down entry
Power-down exit
Self refresh exit
Self refresh
Action
©2006 Micron Technology, Inc. All rights reserved.
5
Commands
Notes
6