MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 97

• Manufacturer Part Number: MT41J256M8HX-15E:D
• Description: MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr
• Series: -r

Specifications of MT41J256M8HX-15E:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 78-TFBGA
• Lead Free Status / RoHS Status: Compliant

REFRESH
Figure 40: Refresh Mode
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
DQS, DQS# 4
Command
Address
BA[2:0]
DM 4
DQ 4
CK#
CKE
A10
CK
NOP 1
T0
Notes:
One bank
All banks
Bank(s) 3
there is no open row in that bank (idle state) or if the previously open row is already in
the process of precharging. However, the precharge period is determined by the last
PRECHARGE command issued to the bank.
REFRESH is used during normal operation of the DRAM and is analogous to CAS#-
before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care” during a REFRESH command. The
DRAM requires REFRESH cycles at an average interval of 7.8µs (maximum when T
85°C or 3.9µs MAX when T
command is registered and ends
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight REFRESH
commands can be posted to any given DRAM, meaning that the maximum absolute
interval between any REFRESH command and the next REFRESH command is nine
times the maximum average interval refresh rate. Self refresh may be entered with up to
eight REFRESH commands being posted. After exiting self refresh (when entered with
posted REFRESH commands) additional posting of REFRESH commands is allowed to
the extent the maximum number of cumulative posted REFRESH commands (both pre
and post self refresh) does not exceed eight REFRESH commands.
The posting limit of eight REFRESH commands is a JEDEC specification; however, as
long as all the required number of REFRESH commands are issued within the refresh
period (64ms), exceeding the eight posted REFRESH commands is allowed.
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
PRE
T1
these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH com-
mands, but may be inactive at other times (see “Power-Down Mode” on page 153).
t CK
NOP 1
T2
t CH
t RP
t CL
NOP 1
T3
C
≤ 95°C). The REFRESH period begins when the REFRESH
REF
T4
97
t
RFC (MIN) later.
t RFC (MIN)
Valid 1
NOP 1
Ta0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
REF 2
Ta1
2Gb: x4, x8, x16 DDR3 SDRAM
Valid 1
NOP 1
Tb0
Indicates A Break in
Time Scale
©2006 Micron Technology, Inc. All rights reserved.
t RFC 2
Valid 1
NOP 1
Tb1
Don’t Care
Commands
Tb2
ACT
RA
RA
BA
C
≤