MT41J256M8HX-15E:D Micron Technology Inc, MT41J256M8HX-15E:D Datasheet - Page 98

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MT41J256M8HX-15E:D

Manufacturer Part Number
MT41J256M8HX-15E:D
Description
MICMT41J256M8HX-15E:D 2GB:X4,X8,X16 DDR3
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Series
-r
Datasheets

Specifications of MT41J256M8HX-15E:D

Organization
256Mx8
Address Bus
18b
Maximum Clock Rate
1.333GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
165mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (256M x 8)
Speed
667MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
78-TFBGA
Lead Free Status / RoHS Status
Compliant

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SELF REFRESH
DLL Disable Mode
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D4.fm - Rev G 2/09 EN
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is
2. Enter self refresh mode after
2. The second REFRESH is not required but depicts two back-to-back REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in the self refresh mode, the DRAM retains data without
external clocking. The self refresh mode is also a convenient method used to enable/
disable the DLL (see “DLL Disable Mode” on page 98) as well as to change the clock
frequency within the allowed synchronous operating range (see “Input Clock Frequency
Change” on page 101). All power supply inputs (including V
maintained at valid levels upon entry/exit and during self refresh mode operation. All
power supply inputs (including V
upon entry/exit and during self refresh mode operation. V
V
If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
• DLL disable mode affects the read data clock-to-data strobe relationship (
• In normal operation (DLL on),
The ODT feature is not supported during DLL disable mode (including dynamic ODT).
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming R
disable mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (
and
clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh (see Figure 41 on page 99):
• V
• V
• The first WRITE operation may not occur earlier than 512 clocks after V
• All other self refresh mode exit timing requirements are met.
DD
WRITE latency (CWL = 6).
but not the read data-to-data strobe relationship (
needed to line the read data up with the controller time domain when the DLL is
disabled.
cycles after the READ command. In DLL disable mode,
cycles after the READ command. Additionally, with the DLL disabled, the value of
t
turned off, and R
DLL.
bank is active (must precharge all active banks).
DQSCK could be larger than
REF
SS
Q/2 while in the self refresh mode under certain conditions:
t
CK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this
< V
DQ is valid and stable prior to CKE going back HIGH
REF
DQ < V
TT
_
NOM
TT
DD
_
NOM
is maintained
MR1[9, 6, 2] and R
and R
98
t
t
MOD has been satisfied.
CK.
REF
t
TT
DQSCK starts from the rising clock edge AL + CL
_
CA and V
WR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
are High-Z), set MR1[0] to “1” to disable the
TT
_
REF
WR
DQ) must be maintained at valid levels
2Gb: x4, x8, x16 DDR3 SDRAM
MR2[10, 9] to “0” while in the DLL
t
DQSQ,
REF
t
DQSCK starts AL + CL - 1
REF
t
DQ may float or not drive
QH). Special attention is
©2006 Micron Technology, Inc. All rights reserved.
CA and V
t
CK [AVG] MAX
REF
Commands
REF
DQ) must be
t
DQ is valid
DQSCK),

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