MT47H128M8HQ-3 L:E TR Micron Technology Inc, MT47H128M8HQ-3 L:E TR Datasheet
MT47H128M8HQ-3 L:E TR
Specifications of MT47H128M8HQ-3 L:E TR
Related parts for MT47H128M8HQ-3 L:E TR
MT47H128M8HQ-3 L:E TR Summary of contents
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... Commercial (0°C ≤ T – Industrial (–40°C ≤ T –40°C ≤ T – Automotive (–40°C ≤ T • Revision Note: 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM 1 ≤ 85°C) C ≤ 95°C; C ≤ 85°C) A ≤ ...
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... Speed 256M4 128M8 64M16 1.875ns -187E 2.5ns -25E 2.5ns - 3ns - 3ns 3.75ns -37E 5ns -5E 2 1Gb: x4, x8, x16 DDR2 SDRAM 800 1066 800 n/a 800 n/a n/a n/a n/a n/a n/a n/a n/a n/a 64 Meg Meg banks 8K A[12:0] (8K) BA[2:0] (8) BA[2:0] (8) A[9:0] (1K) ...
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... For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. Features ...
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... DLL Enable/Disable ................................................................................................................................... 83 Output Drive Strength ................................................................................................................................ 83 DQS# Enable/Disable ................................................................................................................................. 83 RDQS Enable/Disable ................................................................................................................................. 83 Output Enable/Disable ............................................................................................................................... 83 On-Die Termination (ODT) ........................................................................................................................ 84 PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... CKE Low Anytime ...................................................................................................................................... 127 ODT Timing .................................................................................................................................................. 129 MRS Command to ODT Update Delay ........................................................................................................ 131 PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... Table 40: Burst Definition .............................................................................................................................. 79 Table 41: READ Using Concurrent Auto Precharge ........................................................................................ 100 Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 106 Table 43: Truth Table – CKE ......................................................................................................................... 121 PDF: 09005aef821ae8bf Rev DS, DH Derating Values with Differential Strobe ............................................ 1Gb: x4, x8, x16 DDR2 SDRAM and IH) ................................................... and IH) .......................................... and DH ...
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... Figure 47: READ Interrupted by READ ........................................................................................................... 98 Figure 48: READ-to-WRITE ............................................................................................................................ 98 Figure 49: READ-to-PRECHARGE – ...................................................................................................... 99 Figure 50: READ-to-PRECHARGE – ...................................................................................................... 99 PDF: 09005aef821ae8bf Rev .............................................................................................................. .............................................................................................................. ............................................................................................................. ............................................................................................................ 67 t RCD (MIN) .............................................................................. 92 7 1Gb: x4, x8, x16 DDR2 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... DQSQ, QH, and Data Valid Window ................................................. 103 t t DQSQ, QH, and Data Valid Window ..................................................... 104 and DQSCK ......................................................................................... 105 8 1Gb: x4, x8, x16 DDR2 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... Bank active READ WRITE PRE, PRE_A Precharging identify all timing requirements or possible command restrictions such as multibank in- teraction, power down, entry/exit, etc. 9 1Gb: x4, x8, x16 DDR2 SDRAM State Diagram CKE_L Self refreshing REFRESH Refreshing Precharge power- down CKE_L ACT = ACTIVATE ...
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... I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#) ...
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... Any specific requirement takes precedence over a general statement. PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM Functional Description 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. exceeds C is < ...
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... Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory inter- nally configured as a multibank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram ODT CKE Control CK logic CK# CS# RAS# CAS# WE# Refresh Mode 14 counter registers address 17 14 A0–A13, Address 17 BA0– ...
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... I/O gating DM mask logic Bank control 256 logic (x32) Column CK,CK# decoder Column- 8 address 2 counter/ latch COL0, COL1 13 1Gb: x4, x8, x16 DDR2 SDRAM Functional Block Diagrams ODT control CK, CK# COL0, COL1 sw1 sw2 8 DLL 8 sw1 sw2 8 32 Read 8 DRVRS R1 MUX latch ...
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... Column CK, CK# CK out decoder Column- 8 address 2 counter/ latch COL0, COL1 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Functional Block Diagrams ODT control CK, CK# COL0, COL1 sw1 sw2 16 DLL 16 sw1 sw2 16 16 DRVRS ...
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... Rev NC, RDQS#/ NF,DQ6 ss DM, DM/RDQS DQ1 DQ3 NF,DQ4 ref dd ss CKE WE# BA0 BA2 BA1 A10 A12 V RFU dd 15 1Gb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions DQS#/ DQS V Q NF,DQ7 DQ0 DQ2 V Q NF,DQ5 RAS# CK# ODT CAS# CS A11 RFU A13 Micron Technology, Inc ...
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... V Q DQ1 DQ4 V Q DQ3 ref ss CKE WE# BA2 BA0 BA1 A10 A12 RFU dd 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM UDQS#/ UDQS V Q DQ15 DQ8 DQ10 V Q DQ13 LDQS#/ LDQS V Q DQ7 ...
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... CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specif- ic circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides pre- charge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE power-down (row active in any bank) ...
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... ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ0–DQ15, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#, and DM for the x4 ...
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... Reserved for future use: Row address bits A13 (x16 only), A14, and A15. 19 1Gb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... X 6.4 CTR 0.7mm (NOM) nonconductive floating pad 20 1Gb: x4, x8, x16 DDR2 SDRAM 0.25 MIN Ball A1 ID 1.2 MAX Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... X 6.4 0.7mm (NOM) nonconductive floating pad 21 1Gb: x4, x8, x16 DDR2 SDRAM 0.25 MIN Ball A1 ID location 1.20 MAX Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... Rev. O 9/08 EN MHz 25°C, Vout(DC) = VddQ/2, Vout (peak-to-peak) = 0.1V. DM input is grouped C with I/O balls, reflecting the fact that they are matched in loading. any given device. 22 1Gb: x4, x8, x16 DDR2 SDRAM Symbol Min Max Units Notes Cck 1.0 2.0 – Cdck 0. ...
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... TN-00-08, listed in Table 7 (page 25). For designs that are expected to last several years and re- quire the flexibility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. ...
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... Figure 10 (page 24). This case temperature limit is allowed to be exceeded briefly during package reflow, as noted in Micron technical note TN-00-15, “Recommended Sol- dering Parameters.” in Figure 10 (page 24). tion. Length (L) 0.5 (L) 0.5 (W) Width (W) Lmm x Wmm FGBA 24 1Gb: x4, x8, x16 DDR2 SDRAM Min Max Units T –55 150 STG ...
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... DDR2 SDRAM θ JA (°C/W) Airflow = 2m/s θ JB (°C/W) θ JC (°C/W) 36.8 22.7 29.9 22.1 35.7 21.6 28.9 21.5 43.1 30.3 36.4 30 39.3 26 ...
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... Defined by pattern in Table 9 (page 27) Defined by pattern in Table 9 (page 27) 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM -3E -3 -37E 7.5 7.5 7 ...
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... Notes: 2. All banks are being interleaved at 3. Control and address bus inputs are stable during deselects. PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM Electrical Specifications – Idd Parameters t RC (Idd) without violating 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Idd2Q x4 x16 90 Idd2N x4 x16 95 Idd3Pf Fast exit 50 MR12 = 0 Idd3Ps Slow exit 10 MR12 = 1 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM -25E/ -3E/ -25 -3 -37E - 150 135 110 110 110 100 95 90 175 130 ...
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... Idd4R x4 190 x8 210 x16 420 Idd5 x4, x8 265 x16 300 Idd6 x4, x8, x16 7 Idd6L 5 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM -25E/ -3E/ -25 -3 -37E - 145 120 110 90 160 135 ...
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... Idd2P must be derated by 20 percent; Idd3P T C slow must be derated by 30 percent; and Idd6 must be derated by 80 per- cent (Idd6 will increase by this amount if T option is still enabled) 30 1Gb: x4, x8, x16 DDR2 SDRAM -25E/ -3E/ -25 -3 -37E 425 ...
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AC Timing Operating Specifications Table 11: AC Operating Specifications and Conditions Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table; VddQ = +1.8V ±0.1V, Vdd = ...
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... ERR when derating clock-related output timing (see notes 6–10per 19 and 48). Micron requires less derating by allowing t vice output is no longer driving ( RPST) or beginning to drive ( 39 1Gb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications t CK (AVG) MAX (AVG) are the average of any 200 consecu [ABS], CL [ABS]) are not violated ...
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... The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock 19. The DRAM output timing is aligned to the nominal or average clock. Most output param- 20. When DQS is used single-ended, the minimum limit is reduced by 100ps. 21. 22. 23. This is not a device limit. The device will operate with a negative value, but system per- 24 recommended that DQS be valid (HIGH or LOW before the WRITE command. 25. The intent of the “ ...
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... READ command internally latches the READ so that data will output CL later. This parameter is only applicable when t t 533 MHz when RTP = 7.5ns. If RTP/(2 × (MIN) has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal t PRECHARGE command until RAS (MIN) has been satisfied ...
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... DC value. Peak-to-peak AC noise on Vref may not exceed ±2 percent of Vref(DC). This measurement taken at the nearest Vref bypass capacitor. resistors, is expected to be set equal to Vref, and must track variations in the DC level of Vref. 42 1Gb: x4, x8, x16 DDR2 SDRAM AC and DC Operating Conditions t AON (MAX) is when the ODT resistance is fully on. t ...
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... Measure voltage (VM) at tested ball with no load. PDF: 09005aef821ae8bf Rev. O 9/08 EN Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) ball being tested, and then measuring current, I(Vih[AC]), and I(Vil[AC]), respectively. between –40°C and 0° 1Gb: x4, x8, x16 DDR2 SDRAM ODT DC Electrical Characteristics Min Nom Max 120 150 180 40 ...
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... Symbol Min Vih(DC) Vref(DC) + 125 Vil(DC) –300 Symbol Vih(AC) Vih(AC) Vil(AC) Vil(AC) 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Max 1 VddQ Vref(DC) - 125 Min Max 1 Vref(DC) + 250 VddQ 1 Vref(DC) + 200 VddQ –300 Vref(DC) - 250 – ...
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... Figure 12 (page 45). is the true input (CK, DQS) level and Vcp is the complementary input (CK#, DQS#). Vmp(DC) is expected to be approximately 0.5 × VddQ RDQS#, LDQS#, and UDQS# signals. VddQ/2. 45 1Gb: x4, x8, x16 DDR2 SDRAM Max VddQ VddQ VddQ 0.50 × VddQ + 175 950 Vin(dc) MAX 1 ...
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... Numbers in diagram reflect nominal values (VddQ = 1.8V). PDF: 09005aef821ae8bf Rev. O 9/08 EN Input Electrical Characteristics and Operating Conditions 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM © 2004 Micron Technology, Inc. All rights reserved. ...
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... Vil (MAX) minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see out- put IV curves) along a 21Ω load line to define a convenient driver current for measurement. 47 1Gb: x4, x8, x16 DDR2 SDRAM Max 0.50 × VddQ + 125 – ...
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... This is guaranteed by design and characterization. 40°C and 0° Q 25Ω Reference point ) 48 1Gb: x4, x8, x16 DDR2 SDRAM Nom Max – 4 – 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. Units Notes Ω ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 5.63 11.30 16.52 22.19 27.59 32.39 36.45 40.38 44.01 47.01 49.63 51.71 53.32 54 ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 (V) Nom 0.00 –5.63 –11.30 –16.52 –22.19 –27.59 –32.39 –36.45 –40.38 –44.01 –47.01 –49.63 –51.71 –53.32 – ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 2.98 5.99 8.75 11.76 14.62 17.17 19.32 21.40 23.32 24.92 26.30 27.41 28.26 29 ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 –2.98 –5.99 –8.75 –11.76 –14.62 –17.17 –19.32 –21.40 –23.32 –24.92 –26.30 –27.41 –28.26 – ...
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... Voltage Across Clamp (V) 53 1Gb: x4, x8, x16 DDR2 SDRAM Minimum Ground Clamp Current (mA) 0.0 0.0 0.0 0.0 0.0 ...
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... Maximum overshoot area above VddQ (see Figure 20 (page 54)) Maximum undershoot area below VssQ (see Figure 21 (page 54)) Figure 20: Overshoot Vdd/VddQ Vss/VssQ Figure 21: Undershoot Vss/VssQ PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM AC Overshoot/Undershoot Specification -187E -25/-25E 0.50V 0.50V 0.50V 0.50V 0.5 V/ns 0.66 V/ns 0.5 V/ns ...
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... AC level: 2 × Vil(DC × Vih(AC) on the rising edge and 2 × Vil(AC × Vih(DC) on the falling edge. For example, the CK/CK# would be –250mV to +500mV for CK rising edge and would be +250mV to –500mV for CK falling edge. 55 1Gb: x4, x8, x16 DDR2 SDRAM Min Max Units ...
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... Vih(AC)/Vil(AC). For slew rates in between the values listed in Table 28 (page 57) and Table 29 (page 58), the derating values may obtained by linear interpolation. PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating (setup time) and IH (hold time) required is calculated IH (base) value to the Δ ...
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... PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating and IH) CK, CK# Differential Slew Rate 2.0 V/ns 1.5 V/ns Δ t Δ t Δ t Δ t ...
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... DDR2 SDRAM Input Slew Rate Derating and IH) 1.0 V/ns Δ t Δ +210 +154 +203 +149 +193 +143 +180 ...
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... Vref to AC Nominal region line Tangent line Nominal line ΔTF Vss Setup slew rate rising signal 59 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate Vref to AC region ΔTR Setup slew rate Vih(ac) MIN - Vref(dc) = rising signal ΔTR ...
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... CK Vref region Nominal slew rate Vss ΔTR 60 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate DC to Vref region ΔTF Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2004 Micron Technology, Inc. All rights reserved. ...
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... DS and sheet value to the derating value listed in Table 30 (page 61). 61 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal line Tangent line Nominal DC to Vref line region ΔTF Tangent line (Vih[dc] MIN - Vref[dc]) = Δ ...
Page 62
... and DH ) for DDR2-533. Table 35 (page 65) provides the Vref-based fully derated values for the 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating t DS nominal slew rate for nominal slew rate for a t and DH ) for DDR2-400 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 63
... DS and DH . Converting the derated base values from DQ referenced the AC/DC trip points to DQ referenced to Vref is listed in Table 33 (page 64). Ta- 63 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating 1.4 V/ns 1.2 V/ns 1.0 V/ns Δ Δ Δ Δ ...
Page 64
... DDR2 SDRAM Input Slew Rate Derating and and DH -specified values b b- 1.0 V/ns 0.8 V/ns 0.6 V/ ...
Page 65
... Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating 1.0 V/ns 0.8 V/ns 0.6 V/ 370 ...
Page 66
... Tangent line Nominal line ΔTF ΔTR Tangent line (Vref[dc] - Vil[ac] MAX) Tangent line (Vih[ac] MIN - Vref[dc]) Setup slew rate = = rising signal ΔTF 66 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate Vref to AC region Vih(ac) MIN - Vref(dc) = ΔTR t ...
Page 67
... Vref region Tangent line Nominal Vss ΔTR Tangent line (Vref[dc] - Vil[dc] MAX) Hold slew rate = ΔTR falling signal 67 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate DC to Vref region ΔTF Vih(dc) MIN - Vref(dc) = Δ Nominal line Tangent ...
Page 68
... Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MIN Vil(ac) MIN VssQ VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX VssQ © ...
Page 69
... VddQ Crossing point Vswing Vix VssQ 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating V ref VddQ Vih(ac) MIN Vih(dc) MIN Vref(dc) Vil(dc) MAX Vil(ac) MAX VssQ © 2004 Micron Technology, Inc. All rights reserved. ...
Page 70
... H Power-down exit L 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at Notes: 2. The state of ODT does not affect the states described in this table. The ODT function is 3. “X” means “H or L” (but a defined logic level) for valid Idd measurements. ...
Page 71
... A READ burst has been initiated, with auto precharge disabled and has not yet terminated. Write: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated. 71 1Gb: x4, x8, x16 DDR2 SDRAM Command/Action t RP has been met, and any READ burst is com- t RCD has been met ...
Page 72
... NOP commands must be applied on each positive clock edge during these states): Starts with registration of a REFRESH command and ends when Refresh: t met. After RFC is met, the DDR2 SDRAM will be in the all banks idle state. Accessing Starts with registration of the LOAD MODE command and ends when t mode MRD has been met ...
Page 73
... A row in the bank has been activated and No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated with auto precharge disabled and has not yet terminated. 73 1Gb: x4, x8, x16 DDR2 SDRAM Command/Action t RP has been met, and any t RCD has been met. ...
Page 74
... READ with auto precharge WRITE or WRITE with auto precharge DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. PDF: 09005aef821ae8bf Rev. O 9/08 EN ...
Page 75
... If auto precharge is selected, the row being accessed will be pre- charged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to command to the internal device by AL clock cycles. ...
Page 76
... Mode Register (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, operat- ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 34 (page 77) ...
Page 77
... Burst Length Burst length is defined by bits M0–M2, as shown in Figure 34 (page 77). Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being pro- grammable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. ...
Page 78
... Table 40 (page 79). DDR2 SDRAM sup- ports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is supported; however, sequential address ordering is nibble-based. PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM ...
Page 79
... Figure 34 (page 77). When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.” ...
Page 80
... Write Recovery Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 77). The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera- tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter- nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last data burst. An example of WRITE with auto precharge is shown in Figure 63 (page 113). WR values clocks may be used for programming bits M9– ...
Page 81
... DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea- ture allows the READ command to be issued prior to internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further detail in Posted CAS Additive Latency (AL) (page 84). Examples and are shown in Figure 35 (page 81); both assume READ command is registered at clock edge n, and the clocks, the data will be available nominally coincident with clock edge (this assumes ...
Page 82
... OCD operation, all three bits must be set to “1” for the OCD default state, then set to “0” before initialization is finished. 82 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR) t MRD before initiating any subsequent opera- ...
Page 83
... The RDQS ball is enabled by bit E11, as shown in Figure 36 (page 82). This feature is only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored by the DDR2 SDRAM. Output Enable/Disable The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 36 (page 82). ...
Page 84
... In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to using this feature would set held for the time of the AL before it is issued internally to the DDR2 SDRAM device controlled by the sum of AL and CL CL. WRITE latency (WL) is equal to RL minus one clock × ...
Page 85
... ACTIVE n WRITE n Command DQS, DQS Notes PDF: 09005aef821ae8bf Rev NOP NOP NOP AC, DQSCK, and T2 T3 NOP NOP t RCD (MIN 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR NOP NOP NOP Transitioning Data t DQSQ NOP NOP NOP Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 86
... Extended mode register (EMR2) Extended mode register (EMR3) grammed to “0.” served for future use and must be programmed to “0.” 86 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register 2 (EMR2) t MRD before initiating any subsequent opera Address bus ...
Page 87
... Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) programmed to “0.” served for future use and must be programmed to “0.” 87 1Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register 3 (EMR3) t MRD before initiating any subsequent opera Address bus ...
Page 88
... Initialization DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 41 (page 89) illustrates, and the notes outline, the sequence required for power-up and initialization. PDF: 09005aef821ae8bf Rev. O 9/08 EN 1Gb: x4, x8, x16 DDR2 SDRAM 88 Micron Technology, Inc ...
Page 89
Figure 41: DDR2 Power-Up and Initialization VTD ref Tb0 T0 Ta0 LVCMOS SSTL_18 2 low level 2 CKE ...
Page 90
... Rtt (ODT resistance) is off, Vref must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than VddQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). Vtt is not ap- plied directly to the device; however, ...
Page 91
... Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, 13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and 14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af- 15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura- 16 ...
Page 92
... ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. ...
Page 93
... READ Row Col Row Col Bank b Bank b Bank c Bank c t FAW (MIN 3.75ns FAW (MIN) = 37.5ns. 93 1Gb: x4, x8, x16 DDR2 SDRAM ACT READ NOP NOP Row Col Bank d Bank d t RRD (MIN) = 7.5ns, Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 94
... READ burst as long as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of DDR2 SDRAM. As shown in Figure 47 (page 98), READ burst operations may not be interrupted or truncated with any other command except another READ com- mand ...
Page 95
... READ NOP NOP Bank a, Col ( READ NOP NOP Bank a, Col ( AC, DQSCK, and 95 1Gb: x4, x8, x16 DDR2 SDRAM T3 T3n T4 T4n NOP NOP T4n NOP NOP T3n T4 T4n NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 96
... READ Bank, Bank, Col n Col b t CCD READ NOP READ Bank, Bank, Col n Col b t CCD AC, DQSCK, and 96 1Gb: x4, x8, x16 DDR2 SDRAM T5n T3 T3n T4 T4n T5 NOP NOP NOP T5n T2n T3 T3n T4 T4n T5 NOP NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 97
... NOP READ Bank, Bank, Col n Col READ NOP NOP READ Bank, Bank, Col n Col AC, DQSCK, and tive READs. 97 1Gb: x4, x8, x16 DDR2 SDRAM T3n T4 T4n T5 T6 T6n T7 NOP NOP NOP NOP T4n T5 T5n NOP NOP NOP NOP DO n Transitioning Data t DQSQ. ...
Page 98
... T2 can be either same bank or different bank). terrupting READ command NOP NOP WRITE AC, DQSCK, and t RTP is the minimum time from the rising clock edge that initiates the last 4-bit 98 1Gb: x4, x8, x16 DDR2 SDRAM Valid Valid Valid Transitioning Data t CK from previous READ. ...
Page 99
... CK READ NOP NOP NOP AL + BL/2 - 2CK + MAX ( t RTP 2CK) Bank ≥t RAS (MIN) ≥t RC (MIN) t RTP ≥ 2 clocks AC, DQSCK, and 99 1Gb: x4, x8, x16 DDR2 SDRAM t t RTP × CK) where MAX means the larger NOP NOP ACT Bank a Valid ≥ (MIN) Transitioning Data Don’ ...
Page 100
... READ with Auto Precharge If A10 is high when a READ command is issued, the READ with auto precharge function is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock edge that (BL/2) cycles later than the read with auto precharge command provi- t ded edge, the start point of the auto precharge operation will be delayed until satisfied ...
Page 101
... CK NOP 1 NOP 1 READ 2 Col n 5 Bank x t RCD RAS these times. but to when the device begins to drive or no longer drives, respectively. order. 101 1Gb: x4, x8, x16 DDR2 SDRAM T7n T8 NOP 1 PRE 3 NOP 1 NOP 1 t RTP 4 All banks One bank Bank ...
Page 102
... NOP commands are shown for ease of illustration; other commands may be valid at Notes ( the case shown. 3. The DDR2 SDRAM internally delays auto precharge until both 4. Enable auto precharge. 5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level data-out from column n; subsequent elements are applied in the programmed PDF: 09005aef821ae8bf Rev ...
Page 103
... DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. T2 and at T2n are “early DQS,” are “nominal DQS,” and at T3n are “late DQS.” derived from HP 103 1Gb: x4, x8, x16 DDR2 SDRAM T2n T3 T3n DQSQ 2 t DQSQ 2 t DQSQ ...
Page 104
... CH clock transitions collectively when a bank is active. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. lower byte, and UDQS defines the upper byte. 104 1Gb: x4, x8, x16 DDR2 SDRAM T3 T3n ...
Page 105
... I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, WRITE WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL minus one clock cycle ( 1CK) (see READ (page 75)). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
Page 106
... WRITE burst as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architec- ture of DDR2 SDRAM. WRITE burst operations may not be interrupted or truncated with any command except another WRITE command, as shown in Figure 59 (page 109). ...
Page 107
... Rev CK# CK WRITE NOP Bank a, Col b WL ± t DQSS DQSS DQSS 107 1Gb: x4, x8, x16 DDR2 SDRAM T2 T2n T3 T3n T4 NOP NOP NOP DQSS DQSS Transitioning Data Don’t Care t DQSS. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 108
... Bank, Bank, Col b Col n WL ± DQSS CK# CK WRITE NOP NOP Bank, Col b WL ± t DQSS 108 1Gb: x4, x8, x16 DDR2 SDRAM T2n T3 T3n T4 T4n T5 T5n NOP NOP NOP Transitioning Data t DQSS. T2n T3 T3n T4 T4n T5 T5n WRITE NOP NOP Bank, Col n ...
Page 109
... NOP 2 Valid 5 Valid issued to banks used for WRITEs at T0 and T2. starts with T7 and not T5 (because from MR and not the truncated length and T2 can be either same bank or different bank). terrupting WRITE command. 109 1Gb: x4, x8, x16 DDR2 SDRAM NOP 2 NOP 2 Valid 4 Valid ...
Page 110
... WTR is required for any READ following a WRITE to the same device, but it is not re- quired between module ranks. t WTR is referenced from the first positive CK edge after the last data-in pair. greater. 110 1Gb: x4, x8, x16 DDR2 SDRAM NOP READ NOP NOP ...
Page 111
... referenced from the first positive CK edge after the last data-in pair. and WRITE commands may be to different banks, in which case the PRECHARGE command could be applied earlier. 111 1Gb: x4, x8, x16 DDR2 SDRAM NOP NOP NOP t WR Transitioning Data t DQSS not required and Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 112
... Bank x t RCD ± t DQSS (NOM) these times DSH is applicable during DQSS (MIN) and is referenced from T6 DSS is applicable during DQSS (MAX) and is referenced from T7. 112 1Gb: x4, x8, x16 DDR2 SDRAM T5 T5n T6 T6n T7 T8 NOP 1 NOP 1 NOP 1 NOP RAS 5 t DQSL t DQSH t WPST ...
Page 113
... WL ± t DQSS (NOM) t WPRE these times. rounding up to the next integer value DSH is applicable during DQSS (MIN) and is referenced from T6 DSS is applicable during DQSS (MAX) and is referenced from T7. 113 1Gb: x4, x8, x16 DDR2 SDRAM T5 T5n T6 T6n T7 T8 NOP 1 NOP 1 NOP 1 NOP RAS ...
Page 114
... WR starts at the end of the data burst regardless of the data mask condition DSH is applicable during DQSS (MIN) and is referenced from T7 DSS is applicable during DQSS (MAX) and is referenced from T8. 114 1Gb: x4, x8, x16 DDR2 SDRAM T9 T6 T6n T7 T7n T8 NOP 1 NOP 1 NOP RAS ...
Page 115
... DSH (MIN) generally occurs during t DSS (MIN) generally occurs during t RP timing applies. When the PRECHARGE (ALL) com- t RPA timing applies, regardless of the number of banks opened. 115 1Gb: x4, x8, x16 DDR2 SDRAM T3 T3n T4 t DSS 2 t DSH 1 t DSS DQSL t DQSH ...
Page 116
... REFRESH The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in- terval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is registered and ends t RFC (MIN) later. The average interval must be reduced to 3.9µs (MAX) when T ceeds +85° ...
Page 117
... First, the differential clock must be stable and meet prior to CKE going back to HIGH. Once CKE is HIGH ( with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com- mands issued for ments is used to apply NOP or DESELECT commands for 200 clock cycles before applying any other command ...
Page 118
... XSNR is required before any nonREAD command can be applied. ing self refresh at state T1. t XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0. refresh. 118 1Gb: x4, x8, x16 DDR2 SDRAM Tb0 Tc0 Ta2 t ISXR 2 t CKE 3 NOP 4 NOP 4 ...
Page 119
... Figure 69 (page 122)–Figure 76 (page 125). Table 43 (page 121) is the CKE Truth Table. DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is in progress—from the issuing of a READ or WRITE command until completion of the burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined when the read postamble is satisfied ...
Page 120
... XARDS timing is used for exit active power-down to READ command if slow exit is selec- ted via MR (bit 12 = 1). the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting power-down mode for proper READ operation. 120 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode ...
Page 121
... Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE ( was the state of CKE at the 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and action ( result of 4. The state of ODT does not affect the states described in this table. The ODT function is 5. Power-down modes do not perform any REFRESH operations. The duration of power- 6. “ ...
Page 122
... Power-down or self refresh entry may occur after the READ burst completes. PDF: 09005aef821ae8bf Rev NOP NOP Valid entry NOP NOP entry is at T6. 122 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode NOP 1 Valid DO DO Power-down 2 or self refresh entry Transitioning Data NOP 1 Valid Valid DO DO ...
Page 123
... NOP NOP Valid cur later at Ta1, prior to RP being satisfied next integer CK. 123 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode NOP 1 Valid Valid t WTR Power-down or self refresh entry 1 Transitioning Data T5 Ta0 Ta1 Valid 1 Valid NOP WR 2 Power-down or self refresh entry Indicates a break in ...
Page 124
... REFRESH REFRESH command. Precharge power-down entry occurs prior to fied Valid ACT VALID VATE command. Active power-down entry occurs prior to 124 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode T2 T3 NOP t CKE (MIN) Power-down 1 entry Don’t Care t RFC (MIN) being satis NOP ...
Page 125
... PRE Valid All banks A10 vs Single bank CKE 1 x PRECHARGE command. Precharge power-down entry occurs prior to isfied Valid LM Valid 125 1Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode T2 T3 NOP t CKE (MIN Power-down 1 entry Don’t Care NOP NOP t CKE (MIN) t MRD ...
Page 126
... Precharge Power-Down Clock Frequency Change When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must logic LOW level. A minimum of two differential clock cycles must pass after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to change only within minimum and maximum operating frequen- cies specified for the particular speed grade ...
Page 127
... If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be- fore CKE is raised HIGH, at which time the normal initialization sequence must occur (see Figure 41 (page 89)) ...
Page 128
... DO DO System RESET Indicates a break in Unknown time scale represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri- ate configuration (x4, x8, x16). completion of the burst. 128 1Gb: x4, x8, x16 DDR2 SDRAM T5 Ta0 CKE (MIN) 1 NOP 2 4 High-Z High-Z ...
Page 129
... AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0 AXPD (MIN) is not satisfied, AOFPD timing parameters apply. t AXPD (MIN) is satisfied, 129 1Gb: x4, x8, x16 DDR2 SDRAM t AOF timing parameters are applied, as shown t AOFPD timing parameters apply. t AONPD timing parameters apply. t ...
Page 130
... Active power-down slow (asynchronous) Precharge power-down (asynchronous AOND/ AOFD (synchronous AONPD/ AOFPD (asynchronous) 130 1Gb: x4, x8, x16 DDR2 SDRAM Synchronous t t AXPD (8 CKs) First CKE latched HIGH Any mode except self refresh mode t AOND/ Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 131
... MOD window until Valid Valid Valid Valid Valid Valid t AOND t AON (MIN) t AON (MAX) 131 1Gb: x4, x8, x16 DDR2 SDRAM t MOD (MAX) updates the Rtt setting. Ta2 Ta3 Ta4 NOP NOP NOP 2 t MOD t IS Undefined New setting Indicates a break in time scale t MOD is met ...
Page 132
... AOFPD (MIN) Transitioning Rtt NOP NOP NOP NOP t AOFD Transitioning Rtt 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM ODT Timing Valid Valid Valid Valid Valid Valid Valid Valid t AOFPD (MAX) Rtt Unknown ...
Page 133
... T3 NOP NOP NOP NOP t ANPD (MIN) t AOND t AON (MIN) Transitioning Rtt 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb: x4, x8, x16 DDR2 SDRAM ODT Timing NOP NOP NOP t AON (MAX) t AONPD (MAX) t AONPD (MIN) Rtt Unknown Rtt On Don’ ...
Page 134
... PDF: 09005aef821ae8bf Rev Ta0 NOP NOP NOP NOP t AXPD (MIN) Indicates a break in Rtt Unknown time scale 134 1Gb: x4, x8, x16 DDR2 SDRAM Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP t AOFD t AOF (MIN) t AOFPD (MAX) t AOFPD (MIN) Rtt On Transitioning Rtt Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 135
... Rev Ta0 NOP NOP NOP NOP t AXPD (MIN) Indicates a break in RTt Unknown time scale times occur. 135 1Gb: x4, x8, x16 DDR2 SDRAM Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP t AOND t AON (MAX) t AON (MIN) t AONPD (MAX) t AONPD (MIN) Rtt On Transitioning Rtt Micron Technology, Inc ...