K4S641632KUC75 Samsung Semiconductor, K4S641632KUC75 Datasheet

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K4S641632KUC75

Manufacturer Part Number
K4S641632KUC75
Description
Manufacturer
Samsung Semiconductor
Datasheet

Specifications of K4S641632KUC75

Lead Free Status / RoHS Status
Compliant
K4S640832K
K4S641632K
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
64Mb K-die SDRAM Specification
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 14
Rev. 1.1 February 2006
Synchronous DRAM

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K4S641632KUC75 Summary of contents

Page 1

... K4S640832K K4S641632K 64Mb K-die SDRAM Specification INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...

Page 2

... April 2005 0.3 July 2005 1.0 September 2005 1.1 February 2006 - Target spec release - Change DC current - Delete bit organization for x4 - Delete 7ns speed bin - Final spec release - Added 5ns speed bin for x16 Synchronous DRAM History Rev. 1.1 February 2006 ...

Page 3

... K4S640832K K4S641632K 2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & Burst length ( & Full page) -. Burst type (Sequential & ...

Page 4

... TSOP(II) Package Dimension Synchronous DRAM 0~8°C 0.25 TYP 0.010 +0.075 0.125 -0.035 +0.003 0.005 -0.001 1.00 1.20 ± 0.05 ± 0.10 MAX ± 0.002 0.039 ± ...

Page 5

... CLK CKE Samsung Electronics reserves the right to change products or specification without notice. * Data Input Register Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register CS RAS CAS Synchronous DRAM LWCBR LDQM L(U)DQM Rev. 1.1 February 2006 LWE LDQM DQi ...

Page 6

... Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device Synchronous DRAM x16 V SS DQ15 V SSQ DQ14 DQ13 V DDQ ...

Page 7

... DD DDQ V 2 =1.4V ± 200 mV) = 23° 1MHz, V REF Symbol C CLK ADD C OUT Synchronous DRAM Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Max Unit Min Max Unit 2.5 4.0 pF 2.5 5.0 pF 2.5 5.0 pF 4.0 6.5 pF Rev. 1.1 February 2006 ...

Page 8

... Input signals are changed one time during 20ns CKE ≥ V (min), CLK ≤ ∞ (max Input signals are stable Page burst 4Banks Activated t = 2CLKs CCD ≥ (min CKE ≤ 0. DDQ SSQ Synchronous DRAM Version Unit 400 uA Rev. 1.1 February 2006 Note 1 ...

Page 9

... CC N Input signals are changed one time during 20ns CKE ≥ V (min), CLK ≤ V (max Input signals are stable Page burst 4Banks Activated t = 2CLKs CCD ≥ (min CKE ≤ 0. DDQ Synchronous DRAM Version 10ns 15 = ∞ 10ns 30 = ∞ 110 100 85 110 100 ...

Page 10

... RP t (min RAS t (max) 100 RAS t (min (min) 2 RDL t (min) 2 CLK + tRP DAL t (min) 1 CDL t (min) 1 BDL t (min) 1 CCD Synchronous DRAM Unit Vtt = 1.4V 50Ω 50Ω 30pF (Fig output load circuit Unit Note CLK 2,5 CLK 2 CLK 2 CLK Rev. 1.1 February 2006 ...

Page 11

... Measure in linear 1.37 region : 1.2V ~ 1.8V Measure in linear 1.30 region : 1.2V ~ 1.8V Measure in linear 2.8 region : 1.2V ~ 1.8V Measure in linear 2.0 region : 1.2V ~ 1.8V , use these values to design to use these values to design to Synchronous DRAM 60 75 Unit Max Min Max 7.5 1000 1000 5 ...

Page 12

... Max I (mA) 200 155.82 - 153.72 150 148.40 146.02 141.75 100 136.08 131.39 105.84 50 93.66 75.25 49. 0 Synchronous DRAM 200MHz/133MHz Pull-up 1 1.5 2 2.5 3 3.5 Voltage I Min (200MHz / 133MHz Max (200MHz / 133MHz) OH 200MHz/133MHz Pull-down 1 1.5 2 2.5 3 3.5 Voltage I Min (200MHz / 133MHz) ...

Page 13

... Synchronous DRAM Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage I (mA) Rev ...

Page 14

... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...

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