K4H561638F-ULB3 Samsung Semiconductor, K4H561638F-ULB3 Datasheet
K4H561638F-ULB3
Specifications of K4H561638F-ULB3
Related parts for K4H561638F-ULB3
K4H561638F-ULB3 Summary of contents
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free 256Mb F-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Revision 1.2 October, 2004 DDR SDRAM Rev. 1.2 October, 2004 ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free 256Mb F-die Revision History Revision 1.0 (April, 2004) -First release Revision 1.1 (May, 2004) -Modified IDD current spec. Revision 1.2 (October, 2004) -Corrected typo. DDR SDRAM Rev. 1.2 October, 2004 ...
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... Maximum burst refresh cycle : 8 • 66pin TSOP II Pb-Free package • RoHS compliant Ordering Information Part No. K4H561638F-UC/LB3 K4H561638F-UC/LAA K4H561638F-UC/LA2 K4H561638F-UC/LB0 K4H560838F-UC/LB3 K4H560838F-UC/LAA K4H560838F-UC/LA2 K4H560838F-UC/LB0 Operating Frequencies B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 *CL : CAS Latency Org. Max Freq. ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Pin Description DDQ SSQ DDQ SSQ DDQ LDQS LDM WE CAS CAS RAS RAS AP/A AP Organization 16Mx16 DM is internally loaded to match DQ and DQS identically. 16Mb x 16 32Mb DDQ SSQ DDQ 10 NC 66Pin TSOPII 11 3 (400mil x 875mil) ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Package Physical Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) 66pin TSOPII / Package dimension DDR SDRAM Units : Millimeters (10×) (10×) +0.075 0.125 -0.035 ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Block Diagram ( 8Mbit 4Mbit Banks) Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE x16 CK, CK Data Input Register Serial to parallel x32 4Mx16 / 2Mx32 4Mx16 / 2Mx32 4Mx16 / 2Mx32 4Mx16 / 2Mx32 Column Decoder Latency & Burst Length ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input L(U)DM Input BA0, BA1 Input 12] Input DQ I/O L(U)DQS I VDDQ Supply VSSQ Supply VDD Supply VSS Supply VREF Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK ...
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... Burst stop command is valid at every burst length. 8. UDM/LDM sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. CKEn-1 CKEn CS ...
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... Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAM General Description The K4H560838F / K4H561638F is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 4/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, 7.5ns for DDR266, 6ns for DDR333; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 2 ...
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... Normal IDD6 Low power IDD7A 32Mx8 (K4H560838F) AA(DDR266@CL=2. 115 115 160 140 160 135 170 160 3 3 1.5 1.5 280 280 16Mx16 (K4H561638F) AA(DDR266@CL=2. 125 115 200 170 190 165 180 165 3 3 1.5 1.5 350 300 DDR SDRAM (V =2.7V 10°C) DD Unit A2(DDR266@CL=2 ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Notes : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2 ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Power down exit time Exit self refresh to non-Read command Exit self refresh to read command ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate tDS +/- 0.0 V/ns 0 +/- 0.25 V/ns +50 +/- 0.5 V/ns +100 Table 5 : Output Slew Rate Characteristice (X16 Devices only) Typical Range Slew Rate Characteristic ...
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... DQS will be tran sitioning from High logic LOW previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 5. For command/address input slew rate ≥ 1.0 V/ns 6. For command/address input slew rate ≥ ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free b. Pulldown slew rate is measured under the test conditions shown in Figure 2. Output Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching ...
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... DDR SDRAM Output Driver V-I Characteristics DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input into simulation tools ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 51 ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free 0.0 Pullup Characteristics for Weak Output Driver 0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Pulldown Characteristics for Weak Output Driver Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) 1.0 2.0 1.0 2.0 DDR SDRAM ...
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... DDR SDRAM 256Mb F-die (x8, x16) Pb-Free Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 29 ...