MT48LC8M8A2TG-7E IT:G Micron Technology Inc, MT48LC8M8A2TG-7E IT:G Datasheet

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... Notes: 1. Refer to Micron technical note: TN-48-05. Micron Technology, Inc., reserves the right to change products or specifications without notice. 1 64Mb: x4, x8, x16 SDRAM t WR Off-center parting line. 3. Contact Micron for product availability. Part Number Example: MT48LC8M8A2TG-75:G ©2000 Micron Technology, Inc. All rights reserved. Features Marking 16M4 8M8 4M16 ...

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... MHz -75 133 MHz -7E 133 MHz -75 100 MHz Table 3: 64Mb SDRAM Part Numbers MT48LC16M4A2TG MT48LC16M4A2P MT48LC8M8A2TG MT48LC8M8A2P MT48LC4M16A2TG MT48LC4M16A2P MT48LC4M16A2B4 MT48LC4M16A2F4 Notes: 1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron containing 67,108,864 bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’ ...

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... Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. ...

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... Electrical Specifications .44 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Timing Diagrams .52 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAMTOC.fm - Rev. N 12/08 EN 64Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2000 Micron Technology, Inc. All rights reserved. Table of Contents ...

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... WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Figure 53: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Figure 54: 54-Pin Plastic TSOP II (400 mil .71 Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAMLOF.fm - Rev. N 12/ RCD (MIN) When 2 < RCD (MIN)/ 5 64Mb: x4, x8, x16 SDRAM List of Figures t CK ≤ ...

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... List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 3: 64Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Table 4: Pin/Ball Descriptions .11 Table 5: Burst Definition .16 Table 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 7: Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 9: Truth Table 3 – Current State Bank n, Command to Bank .40 Table 10: Truth Table 4 – ...

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... CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 10 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 1,024 x 4) DECODER SENSE AMPLIFIERS 4096 I/O GATING ...

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... CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 9 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 512 x 8) DECODER SENSE AMPLIFIERS 4096 I/O GATING ...

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... CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 8 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ BANK0 ROW- 12 ROW- ADDRESS BANK0 ADDRESS MUX MEMORY 4096 LATCH ARRAY & (4,096 x 256 x 16) DECODER SENSE AMPLIFIERS 4096 I/O GATING ...

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... DQ14 C DQ12 D DQ10 E DQ8 F DQMH G NC/A12 Notes: 1. The balls at A4, A5, and A6 are absent from the physical package. They are included to illus- trate that rows 4, 5, and 6 exist, but contain no solder balls. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN x16 - DQ0 DQ1 4 51 ...

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... Rev. N 12/08 EN Pin/Ball Assignments and Descriptions Type Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal ...

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... V SS Functional Description In general, the 64Mb SDRAM (4 Meg banks, 2 Meg banks, and 1 Meg banks quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the x8’ ...

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... REFRESH + Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CL, an operating mode and a write burst mode, as shown in Figure 6 on page 15. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored infor- mation until it is programmed again or the device loses power. Mode register bits M0– ...

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... Burst Length READ and WRITE accesses to the SDRAM are burst oriented, with the burst length (BL) being programmable, as shown in Figure 6 on page 15. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command ...

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... Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 5 on page 16. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN A11 ...

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... DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 7 on page 17. Table 6 on page 17 indicates the oper- ating frequencies at which each CL setting can be used. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN Starting Column Address 2 A0 ...

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... Write Burst Mode When the burst length programmed via M0–M2 applies to both read and write bursts; when the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ NOP ...

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... SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...

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... This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ RP) after the precharge command is issued. Input A10 determines Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. ...

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... The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for required for the completion of any internal refresh in progress ...

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... CL setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN CLK CKE HIGH CS# ...

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... CL -1. This is shown in Figure 12 on page 25 for and data element either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command ...

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... Figure 11: CAS Latency COMMAND COMMAND PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ NOP CLK READ NOP 64Mb: x4, x8, x16 SDRAM T2 T3 NOP OUT NOP NOP OUT t AC DON’T CARE UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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... Figure 12: Consecutive READ Bursts COMMAND ADDRESS COMMAND ADDRESS Note: Each READ command may be to any bank. DQM is LOW. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ NOP NOP BANK, COL n D OUT DQ n CAS Latency = CLK READ NOP NOP BANK, COL n ...

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... READ burst, provided that I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...

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... If a burst of one is used, then DQM is not required. Figure 15: READ-to-WRITE With Extra Clock Cycle DQM COMMAND ADDRESS Note used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ NOP NOP BANK, COL n ...

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... CL = -1. This is shown in Figure 17 on page 29 for each possible CL; data element the last desired data element of a longer burst. Figure 16: READ-to-PRECHARGE COMMAND ADDRESS COMMAND ADDRESS Note: DQM is LOW. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ met. Note that part of the row precharge time CLK READ NOP NOP ...

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... WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ ...

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... An example is shown in Figure 20 on page 31. Data either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. ...

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... The disadvan- tage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ WRITE ...

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... Each WRITE command may be to any bank. DQM is LOW. Figure 22: WRITE-to-READ CLK COMMAND ADDRESS Note: The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW for illustration. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ WRITE WRITE WRITE WRITE BANK, ...

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... BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ ...

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... HIGH at the desired clock edge (meeting Figure 24: Terminating a WRITE Burst COMMAND ADDRESS Note: DQMs are LOW. Figure 25: PRECHARGE Command CLK CKE CS# RAS# CAS# WE# A0–A9 A10 BA0,1 PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ REF CLK BURST NEXT WRITE TERMINATE COMMAND BANK, (ADDRESS) COL (DATA) ...

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... In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ ...

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... Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. ...

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... WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 32 on page 39). Figure 29: READ With Auto Precharge Interrupted by a READ Internal States Note: DQM is LOW. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ met, where met, where WR begins when the WRITE to bank m is registered. The last T0 T1 ...

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... READ With Auto Precharge Interrupted by a WRITE Internal States Notes: 1. DQM is HIGH prevent D Figure 31: WRITE With Auto Precharge Interrupted by a READ Internal States Notes: 1. DQM is LOW. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CLK READ - AP COMMAND NOP NOP BANK n Page BANK n READ with Burst of 4 ...

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... H Notes: 1. CKE clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND COMMAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided that 6 ...

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... Refreshing: Starts with registration of an AUTO REFRESH command and ends when met. After RC is met, the SDRAM will be in the all banks idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 40 64Mb: x4, x8, x16 SDRAM Command (Action) ...

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... RP is met. After RP is met, all banks will be in the idle state. Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 64Mb: x4, x8, x16 SDRAM Commands t MRD is met, the SDRAM will be in the all ©2000 Micron Technology, Inc. All rights reserved. ...

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... AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN CAS# WE COMMAND INHIBIT (NOP/continue previous operation) ...

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... WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to bank n will begin after tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 32 on page 39). PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN 64Mb: x4, x8, x16 SDRAM met, where WR begins when the WRITE to bank m is regis- Micron Technology, Inc ...

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... Storage temperature (plastic) Power dissipation Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Figure 12 on page 45, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’ ...

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... For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN Symbol ...

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... Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View Test point Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View Test point PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN 22.22mm 11.11mm 8.00mm 4.00mm 8.00mm 4.00mm Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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... Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQs Table 17: VFBGA Capacitance Note 2 applies to entire table; notes appear on pages 50 and 51 Parameter Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQs PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN Symbol ...

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... Refresh period (4,096 rows) Refresh period–Automotive (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH-to-ACTIVE command PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ -7E Symbol Min Max Min t AC(3) – 5.5 – ...

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... Last data-in to burst stop command Last data-in to new READ/WRITE command Last data-in to precharge command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from precharge command PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN 64Mb: x4, x8, x16 SDRAM Electrical Specifications Symbol -6 -7E t CCD ...

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... The I frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ dependent on output loading and cycle rates. Specified values are obtained ≤ ...

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... CK = 6ns. 33. CKE is HIGH during refresh command period limit is actually a nominal value and does not result in a fail value. 34. The -6 speed grade does not support PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ for a pulse width ≤ 3ns, and the pulse width overshoot: V (MAX ...

Page 52

... If CS# is HIGH at clock HIGH time, all commands applied are NOP. 2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after command is issued. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ ...

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... CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes: 1. Violating refresh requirements during power-down may result in a loss of data. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CKS ( ( ) ) ( ( ...

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... BA0, BA1 BANK DQ Notes: 1. For this example and auto precharge is disabled. 2. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ NOP NOP NOP t AC ...

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... CMH COMMAND PRECHARGE DQM / DQML, DQMH A0–A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ AUTO ...

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... AS AH BA0, BA1 BANK(S) High-Z DQ Precharge all active banks Notes maximum time limit for self refresh mode XSR requires minimum of two clocks regardless of frequency and timing. 3. Self refresh mode not supported on automotive temperature (AT) devices. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ CKS ≥ ...

Page 57

... Notes: 1. For this example and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ READ NOP ...

Page 58

... BANK DQ t RCD t RAS t RC Notes: 1. For this example and x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ READ NOP NOP t CMS t CMH ...

Page 59

... For this example and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” 3. PRECHARGE command not allowed or PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ READ ...

Page 60

... RAS t RC Notes: 1. For this example and READ command not allowed or 3. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ NOP 2 NOP 2 READ ...

Page 61

... RAS - BANK BANK 0 t RRD Notes: 1. For this example and x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ READ NOP ACTIVE t CMS t CMH ...

Page 62

... BANK DQ t RCD Notes: 1. For this example x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” 3. Page left open; no PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ READ NOP NOP NOP t CMH ...

Page 63

... BA0, BA1 BANK DQ t RCD Notes: 1. For this example and x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ READ NOP NOP t CMS t CMH ...

Page 64

... For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <D frequency. 3. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ WRITE ...

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... BANK RCD t RAS t RC Notes: 1. For this example x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ WRITE NOP NOP NOP t CMH BANK t DH ...

Page 66

... For this example and the WRITE burst is followed by a “manual” PRECHARGE. 2. 15ns is required between <D frequency. 3. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” 4. PRECHARGE command not allowed or PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ NOP 4 NOP 4 ...

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... RCD t RAS t RC Notes: 1. For this example x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” 3. WRITE command not allowed or PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ NOP 3 NOP 3 WRITE NOP ...

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... RAS - BANK BANK 0 t RRD Notes: 1. For this example x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ WRITE NOP ACTIVE NOP t CMH ROW ...

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... RCD Notes: 1. x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” must be satisfied prior to PRECHARGE command. 3. Page left open; no PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ WRITE NOP NOP t CMH t CMS ...

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... AH BA0, BA1 BANK DQ t RCD Notes: 1. For this example x16: A8, A9 and A11 = “Don’t Care” x8: A9 and A11 = “Don’t Care” x4: A11 = “Don’t Care” PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/ NOP WRITE NOP t CMS t CMH ...

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... Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN 22.22 ±.08 2X 0.71 2X 0.10 2.80 +0.10 0.10 -0.05 SEE DETAIL A Micron Technology, Inc ...

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... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80725c0b/Source: 09005aef806fc13c 64MSDRAM_2.fm - Rev. N 12/08 EN 6.40 0.80 ...