CY7C464A-10JI QP SEMICONDUCTOR, CY7C464A-10JI Datasheet - Page 8

no-image

CY7C464A-10JI

Manufacturer Part Number
CY7C464A-10JI
Description
Manufacturer
QP SEMICONDUCTOR
Datasheet

Specifications of CY7C464A-10JI

Lead Free Status / RoHS Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C464A-10JI
Manufacturer:
CYPRESS
Quantity:
1 480
Part Number:
CY7C464A-10JI
Manufacturer:
CY
Quantity:
190
Part Number:
CY7C464A-10JI
Manufacturer:
CYPRESS
Quantity:
1 054
Part Number:
CY7C464A-10JI
Manufacturer:
INTERSIL
Quantity:
45
Architecture
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF), and Full flags (FF) being HIGH. Read (R) and Write
(W) must be HIGH t
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
appearing at the inputs (D
rising edge of W will be stored sequentially in the FIFO.
The EF LOW-to-HIGH transition occurs t
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW t
ally being half full. Therefore, the HF is active once the FIFO
is filled to half its capacity plus one word. HF will remain LOW
while less than one half of total memory is available for writing.
The LOW-to-HIGH transition of HF occurs t
edge of R when the FIFO goes from half full +1 to half full. HF
Document #: 38-06011 Rev. *A
Switching Waveforms
Note:
13. Expansion out of device 1 (XO
Expansion TimingDiagrams
XO
XO
WHF
1
1
(XI
(XI
Q
D
0
2
0
2
after the falling edge of W following the FIFO actu-
)
)
[13]
D
[13]
W
Q
R
8
8
RPW
/t
WPW
0
1
D
[7]
) is connected to expansion in of device 2 (XI
t
before and t
LZR
8
) t
(continued)
SD
t
XOL
t
A
before and t
t
XOL
RMR
WEF
RHF
after the rising
after the rising
after the first
HD
t
DATA
VALID
DVR
DATA VALID
after the
t
SD
t
RR
2
t
).
t
XOH
HD
t
WR
is available in standalone and width expansion modes. FF
goes LOW t
which the last available location is filled. Internal logic prevents
overrunning a full FIFO. Writes to a full FIFO are ignored and
the write pointer is not incremented. FF goes HIGH t
a read from a full FIFO.
Reading Data from the FIFO
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q
tween read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty
FIFO are ignored and do not increment the read pointer. From
the empty condition, the FIFO can be read t
write.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
(RT) input is active in the standalone and width expansion
modes. The retransmit feature is intended for use when a
t
XOH
WFF
t
A
0
after the falling edge of W, during the cycle in
Q
8
) are in a high-impedance condition be-
CY7C460A/CY7C462A
CY7C464A/CY7C466A
DATA VALID
t
SD
VALID
DATA
t
DVR
t
HD
t
HZR
WEF
Page 8 of 15
after a valid
RFF
C460A–15
C460A–16
after

Related parts for CY7C464A-10JI