M25P80-VMP6G Micron Technology Inc, M25P80-VMP6G Datasheet
M25P80-VMP6G
Specifications of M25P80-VMP6G
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M25P80-VMP6G Summary of contents
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... April 2010 ® Forté™ Serial Flash Memory 8 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface SO8W (MW) 208 mils width (MLP8) PDIP8 (BA) 300 mils width Rev 23 M25P80 SO8 (MN) 150 mils width VFDFPN8 (MP) UFDFPN8 (MC) (MLP8 mm) 1/57 www.numonyx.com 1 ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Description The M25P80 Mbit (1 Mbit × 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide ...
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... VFQFPN, SO8, and PDIP8 connections 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally and must not be allowed to be connected to any other voltage or signal line on the PCB See Package mechanical section for package dimensions, and how to identify pin-1. M25P80 ...
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Signal description 2.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data input (D) This input ...
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V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC 9/57 ...
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... Serial Data Output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P80 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at ...
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Example pF, that is R*C p never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 4. SPI modes supported CPOL CPHA ...
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Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P80 boasts the following data protection mechanisms: Power-On Reset and an internal timer (t inadvertent changes while the power supply is outside the operating specification. ...
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Table 2. Protected area sizes Status Register content BP2 BP1 BP0 bit bit bit The device is ready to accept a Bulk Erase instruction only if all ...
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Figure 5. Hold condition activation C HOLD (standard use) Hold Condition (non-standard use) Hold Condition AI02029D 15/57 ...
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Memory organization The memory is organized as: 1,048,576 bytes (8 bits each) 16 sectors (512 Kbits or 65,536 bytes each) 4096 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The ...
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Figure 6. Block diagram HOLD W Control Logic Address Register and Counter High Voltage Generator I/O Shift Register 256 Byte Data Buffer FFFFFh 00000h 000FFh 256 Bytes (Page Size) X Decoder Status Register Size of the ...
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Instructions All instructions, addresses, and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven ...
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Table 4. Instruction set Instruction Release from Deep Power- down, and Read Electronic Signature RES Release from Deep Power- down 1. The RDID instruction is available only for parts made with 110 nm Technology identified with Process letter '4'. (Details ...
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Figure 8. Write Disable (WRDI) instruction sequence 20/ Instruction D High Impedance AI03750D ...
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Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: Manufacturer identification (one byte) Device identification (two bytes) A Unique ID code (UID) followed by 16 bytes of CFI data The manufacturer identification is ...
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Figure 9. Read Identification (RDID) instruction sequence and data-out sequence 22/57 ...
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Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. ...
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Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Q 24/ Instruction Status Register Out 7 6 ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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Table 7. Protection modes W SRWD Mode signal bit Software Protected (SPM Hardware 0 1 Protected (HPM defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status ...
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Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising ...
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Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) ...
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Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the ...
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Figure 14. Page Program (PP) instruction sequence Data Byte MSB 1. Address bits A23 to A20 are Don’t Care. 30/ ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the ...
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... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P80 is 13h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction ...
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... Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature for the M25P80 is 13h. Figure 19. Release from Deep Power-down (RES) instruction sequence Instruction D High Impedance Dummy Bytes ...
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Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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Figure 20. Power-up timing (max) Program, Erase and Write commands are Rejected by the device Chip selection Not Allowed V CC (min) Reset State of the device V WI Table 8. Power-up timing and V Symbol ...
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Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 14. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 I Deep Power-down current CC2 I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 ...
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Table 15. AC characteristics (75 MHz operation) 75 MHz available only for products made in 110 nm technology, Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, ...
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Table 15. AC characteristics (75 MHz operation) (continued) 75 MHz available only for products made in 110 nm technology, Test conditions specified in Symbol Alt. t Write Status Register cycle time W Page Program cycle time (256 byte) Page Program ...
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Table 16. AC characteristics (25 MHz operation) Test conditions specified in Symbol Alt. Clock frequency for the following instructions FAST_READ, PP, SE, BE, DP, RES, WREN WRDI, RDSR, WRSR f Clock frequency for READ instructions R ...
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Figure 22. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL High Impedance Q 44/57 tSLCH tCHSH tCHDX tCLCH ...
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Figure 24. Hold timing HOLD Figure 25. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN tHLCH tCHHL tCHHH tHLQZ tHHQX tCH tCLQV tHHCH AI02032 tCL tSHQZ LSB OUT tQLQH tQHQL AI01449e 45/57 ...
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Package mechanical Figure 26. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6 × 5 mm, package outline Drawing is not to scale. 2. The circle in the top ...
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Figure 27. SO8 wide – 8 lead Plastic Small Outline, 208 mils body width, package outline Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows ...
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Figure 28. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline A2 1. Package is not to scale. Table 19. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol Typ ...
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Figure 29. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package outline Package is not to scale. Table 20. PDIP8 – 8 lead Plastic Small Outline, 300 mils body width, package ...
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Figure 30. UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package no lead, 4X3 mm package mechanical data 1. Drawing is not to scale. 50/57 ...
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Table 21. UFDFPN (MLP8) 8-lead ultra thin fine pitch dual flat package no lead, 4X3 mm package mechanical data Databook (mm) Symbol Typ Min A 0.55 0.45 A1 0.02 0.00 A3 — 0.127 θ — D2 0.80 0.70 E2 0.20 ...
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... QNEE9801. Please ask your Numonyx sales office for a copy. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 52/57 Example: M25P80 – ...
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... Available only for Automotive product. Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. M25P80 – (2) 6 ...
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Revision history Table 24. Document revision history Date Revision 24-Apr-2002 1.0 27-Sep-2002 1.1 13-Dec-2002 1.2 24-Oct-2003 2.0 24-Nov-2003 2.1 21-Apr-2004 3.0 07-May-2004 4.0 18-May-2004 5.0 05-Aug-2004 6.0 01-Aug-2005 7.0 20-Oct-2005 8.0 13-Apr-2006 9 20-Jul-2006 10 54/57 Changes Document released ...
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Table 24. Document revision history Date Revision Endurance and data retention information added to Features. 50 MHz frequency added, Instruction times characteristics (40 MHz operation, Grade 6) and characteristics (25MHz 22-Sep-2006 11 in Table 15: AC characteristics (40 MHz operation, ...
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Table 24. Document revision history Date Revision 19-Feb-2009 19 3-August- 20 2009 2-Feb-2010 21 23-Feb-2010 22 14-April- 23 2010 56/57 Changes Made the followng changes: added a bullet to cover page, stating "Automotive Certified Parts Available" Revised part numbering, including ...
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... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash® and Numonyx® Forté™ Serial Flash Memory are trademarks or registered trademarks of Numonyx or its subsidiaries *Other names and brands may be claimed as the property of others. ...