MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 12

no-image

MT29F8G08ABABAWP:B

Manufacturer Part Number
MT29F8G08ABABAWP:B
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08ABABAWP:B

Lead Free Status / RoHS Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT29F8G08ABABAWP:B
Manufacturer:
SPANSION
Quantity:
4 310
Part Number:
MT29F8G08ABABAWP:B
Manufacturer:
MICRON
Quantity:
11 200
Part Number:
MT29F8G08ABABAWP:B
Manufacturer:
MICRON
Quantity:
4 000
Part Number:
MT29F8G08ABABAWP:B
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT29F8G08ABABAWP:B
Manufacturer:
MICRON
Quantity:
15 146
Company:
Part Number:
MT29F8G08ABABAWP:B
Quantity:
3 500
Table 1:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
(R/B2#,R/B3#,R/B4#)
(CE2#,CE3#,CE4#)
(DQ[7:0]-2)
(I/O[7:0]-2)
I/O[7:0]-1,
DQ[7:0]-1
(WE#-2)
(WP#-2)
(ALE-2)
(CLE-2)
I/O[7:0],
(RE#-2)
DQ[7:0]
WE#-1,
WP#-1,
Async
ALE-1,
CLE-1,
RE#-1,
WE#,
WP#,
R/B#,
VccQ
VssQ
DNU
ALE,
CE#,
CLE,
RE#,
RFU
N/A
Vcc
Vss
NC
3
3
3
Signal Definitions
3
3
3
3
Symbol
3
Notes:
3
(R/B2#,R/B3#,R/B4#)
1
(DQ[7:0]-2)
(I/O[7:0]-2)
DQ[7:0]-1,
(W/R#-2)
(WP#-2)
1. See “Device and Array Organization” on page 14 for detailed signal connections.
2. See “Bus Operation” on page 16 for detailed asynchronous and synchronous interface sig-
3. These signals are currently NC and are shown for future placement.
(ALE-2)
DQ[7:0],
(CLE-2)
(CLE-2)
W/R#-1,
(CE2#)
WP#-1,
DQS-1,
ALE-1,
CLE-1,
DQS-2
CLK-1,
W/R#,
Sync
DQS,
WP#,
R/B#,
VccQ
VssQ
DNU
ALE,
CLK,
CE#,
CLE,
RFU
Vcc
Vss
NC
nal-use explanations.
3
3
3
3
3
3
3
3
3
Micron Confidential and Proprietary
Output Ready/busy: An open-drain, active-low output that requires an
Supply Vcc: Core power supply
Supply VccQ: I/O power supply
Supply Vss: Core ground connection
Supply VssQ: I/O ground connection
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
8Gb Asychronous/Synchronous NAND Flash Memory
Address latch enable: Loads an address from I/O[7:0], DQ[7:0] into
the address register.
Chip enable: A signal that enables or disables one or more LUNs in a
target
Command latch enable: Loads a command from I/O[7:0], DQ[7:0]
into the command register.
Data inputs/outputs: The bidirectional I/Os transfer address, data,
and command information.
Data strobe: Provides a synchronous reference for data input and
output.
Read enable and write/read: RE# transfers serial data from the
NAND Flash to the host system when the asynchronous interface is
active. When the synchronous interface is active, W/R# controls the
direction of DQ[7:0] and DQS.
Write enable and clock: WE# transfers commands, addresses, and
serial data from the host system to the NAND Flash when the
asynchronous interface is active. When the synchronous interface is
active, CLK latches command and address cycles.
Write protect: WP# is a signal that enables or disables array
PROGRAM and ERASE operations.
external pull-up resistor. This signal indicates target array activity.
No connect: NCs are not internally connected. They can be driven or
left unconnected.
Do not use: DNUs must be left unconnected.
Reserved for future use: RFUs must be left unconnected.
1
12
.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
2
General Description
©2008 Micron Technology, Inc. All rights reserved.
Advance

Related parts for MT29F8G08ABABAWP:B