MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 19

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MT29F8G08ABABAWP:B

Manufacturer Part Number
MT29F8G08ABABAWP:B
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08ABABAWP:B

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Figure 11:
Asynchronous Data Output
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
I/Ox, DQx
WE#
ALE
CE#
CLE
Asynchronous Data Input Cycles
Data can be output from a LUN if it is in a READY state. Data output is supported
following a READ operation from the NAND Flash array.
Data is output from the cache register of the selected LUN to I/O[7:0], DQ[7:0] on the
falling edge of RE# when:
• CE# is LOW,
• ALE is LOW,
• CLE is LOW, and
• WE# is HIGH.
If the host controller is using a
rising edge of RE# (see Figure 12 on page 20).
If the host controller is using a
next falling edge of RE# [see Figure 13 on page 20 for extended data output (EDO)
timing].
Using the SELECT LUN WITH STATUS (78h) command prevents data contention
following a multi-LUN operation. Once a SELECT LUN WITH STATUS (78h) command
has been issued to a LUN, then issue the READ MODE (00h) command. Data can now be
output from the selected LUN.
Data output requests are typically ignored by a LUN that is busy; however, it is possible
to output data from the status register even when a LUN is busy by first issuing the READ
STATUS or SELECT LUN WITH STATUS (78h) command.
t ALS
t WP
t DS
D
Micron Confidential and Proprietary
IN
t WC
M
t DH
8Gb Asychronous/Synchronous NAND Flash Memory
t WH
t WP
19
t
t
D
RC of 30ns or greater, the host can latch the data on the
RC of less than 30ns, the host can latch the data on the
t DS
IN
M+1
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WP
t DS
D
IN
t CLH
N
t DH
t CH
©2008 Micron Technology, Inc. All rights reserved.
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