MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 25

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Synchronous Interface
Table 4:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Mode
Standby
Bus idle
Bus driving
Command input
Address input
Data input
Data output
Write protect
Undefined
Undefined
Synchronous Interface Mode Selection
Notes:
CE#
H
X
L
L
L
L
L
L
L
L
1. CLK can be stopped when the target is disabled, even when R/B# is LOW.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Commands and addresses are latched on the rising edge of CLK.
When the synchronous interface is activated on a target (see “Activating the Synchro-
nous Interface” on page 37), the target is capable of high-speed DDR data transfers.
Existing signals are redefined for high-speed DDR I/O. The WE# signal becomes CLK.
DQS is enabled. The RE# signal becomes W/R#.
CLK provides a clock reference to the NAND Flash device.
DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND Flash
device. During data input, DQS is controlled by the host controller while inputting data
on DQ[7:0].
The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R#
signal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is
latched LOW, the NAND Flash is driving the DQ bus and DQS.
The synchronous interface bus modes are summarized in Table 4.
CLE
H
H
H
H
X
X
L
L
L
L
Micron Confidential and Proprietary
ALE
H
H
H
H
X
X
L
L
L
L
8Gb Asychronous/Synchronous NAND Flash Memory
CLK
X
X
25
1
W/R#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
X
L
L
L
L
output
note 5
DQS
X
X
X
X
X
X
X
DQ[7:0]
X
X
X
X
X
X
X
X
X
X
©2008 Micron Technology, Inc. All rights reserved.
0V/VccQ
Bus Operation
WP#
H
H
H
X
X
X
X
X
L
2
Advance
Notes
3
3
4
5