MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 26

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Synchronous Enable/Standby
Synchronous Bus Idle/Driving
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
4. During data input to the device, DQS is the “clock” that latches the data in the cache regis-
5. During data output from the NAND Flash device, DQS is an output generated from CLK
6. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V
In addition to the description in the section “Asynchronous Enable/Standby” on
page 16, the following requirements also apply when the synchronous interface is active.
Before enabling a target, CLK must be running and ALE and CLE must be LOW. When
CE# is driven LOW, all of the signals for the selected target are enabled. The target is not
enabled until
Prior to disabling a target, the target's bus must be idle (see “Synchronous Bus Idle/
Driving” on page 26). A target is disabled when CE# is driven HIGH, even when it is busy.
All of the target's signals are disabled except CE#, WP#, and R/B#. After the target is
disabled, CLK can be stopped.
A target enters low-power standby when it is disabled and is not busy. If the target is busy
when it is disabled, the target enters standby after all of the LUNs complete their opera-
tions.
A target's bus is idle or driving when:
• CLK is running,
• CE# is LOW,
• ALE is LOW, and
• CLE is LOW.
The bus is idle when W/R# transitions HIGH and is latched by CLK. During the bus idle
mode, all signals are enabled; DQS and DQ[7:0] are inputs. No commands, addresses, or
data are latched into the target; no data is output. When entering the bus idle mode, the
host must wait a minimum of
the only valid bus modes supported are: bus driving, command, address, and DDR data
input.
The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus
driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH,
but no valid data is output. Following the bus driving mode, the only valid bus modes
supported are bus idle and DDR data output.
ter.
after
V
IL
.
t
DQSCK delay.
Micron Confidential and Proprietary
t
CS completes; the target's bus is then idle.
8Gb Asychronous/Synchronous NAND Flash Memory
26
t
CAD before changing the bus mode. In the bus idle mode,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Bus Operation
Advance
IH
or