MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 28

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Synchronous Commands
Figure 21:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Synchronous Command Cycle
Notes:
A command is written from DQ[7:0] to the command register on the rising edge of CLK
when:
• CE# is LOW,
• ALE is LOW,
• CLE is HIGH, and
• W/R# is HIGH.
After a command is latched, and prior to issuing the next command, address, or data
I/O, the bus must go to the bus idle mode on the next rising edge of CLK, except when
the clock period,
Commands are typically ignored by LUNs that are busy; however, some commands,
such as READ STATUS (70h) and SELECT LUN WITH STATUS (78h), are accepted by
LUNs, even when they are busy (see Table 5 on page 39).
1. When CE# remains LOW,
DQ[7:0]
W/R#
mand cycle is latched for subsequent command, address, data input, or data output cycle(s).
DQS
CE#
ALE
CLK
CLE
Micron Confidential and Proprietary
t
CK, is greater than
8Gb Asychronous/Synchronous NAND Flash Memory
t CALS
t CALS
t CALS
t CS
t CKL
t
CAD begins at the rising edge of the clock from which the com-
t CK
28
t CKH
t DQSHZ
t
CAD.
t CAD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Undefined
t CALS
COMMAND
t CAS
t CALH
t CAH
t CALH
t CAD starts here
t CALS
©2008 Micron Technology, Inc. All rights reserved.
Don’t Care
t CALH
t CALH
t CH
1
Bus Operation
Advance