MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 29

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Synchronous Addresses
Figure 22:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Synchronous Address Cycle
Notes:
A synchronous address is written from DQ[7:0] to the address register on the rising edge
of CLK when:
• CE# is LOW,
• ALE is HIGH,
• CLE is LOW, and
• W/R# is HIGH.
After an address is latched, and prior to issuing the next command, address, or data I/O,
the bus must go to the bus idle mode on the next rising edge of CLK, except when the
clock period,
Bits not part of the address space must be LOW (see Table 2 on page 23). The number of
ADDRESS cycles required for each command varies. Refer to the command descriptions
to determine addressing requirements (see Table 5 on page 39).
Addresses are typically ignored by LUNs that are busy; however, some addresses such as
address cycles that follow the SELECT LUN WITH STATUS (78h) command, are accepted
by LUNs, even when they are busy (see Table 5 on page 39).
1. When CE# remains LOW,
DQ[7:0]
mand cycle is latched for subsequent command, address, data input, or data output cycle(s).
W/R#
DQS
CE#
ALE
CLK
CLE
t
Micron Confidential and Proprietary
CK, is greater than
8Gb Asychronous/Synchronous NAND Flash Memory
t CALS
t CALS
t CALS
t CS
t CKL
t
CAD begins at the rising edge of the clock from which the com-
t CK
29
t CKH
t DQSHZ
t
CAD.
t CAD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Undefined
t CALS
t CAS
ADDRESS
t CALH
t CAH
t CALH
t CAD starts here
t CALS
©2008 Micron Technology, Inc. All rights reserved.
Don’t Care
t CALH
t CALH
t CH
1
Bus Operation
Advance