MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 30

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Synchronous DDR Data Input
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
To enter the DDR data input mode, the following conditions must be met:
• CLK is running,
• CE# is LOW,
• W/R# is HIGH,
•
• DQS is LOW, and
• ALE and CLE are HIGH on the rising edge of CLK.
Upon entering the DDR data input mode after
cache register on each and every rising and falling edge of DQS (center-aligned) when:
• CLK is running and the DQS-to-CLK skew meets
• CE# is LOW,
• W/R# is HIGH, and
• ALE and CLE are HIGH on the rising edge of CLK.
To exit DDR Data Input mode the following conditions must be met:
• CLK is running and the DQS-to-CLK skew meets
• CE# is LOW,
• W/R# is HIGH,
• ALE and CLE are latched LOW on the rising edge of CLK,
• The final two data bytes of the data input sequence are written from DQ[7:0] to the
• After the final falling edge of DQS, it is held low for
Following
of CLK. After
Data input is ignored by LUNs that are not selected or are busy.
t
cache register on the final rising and falling edges of DQS after the last cycle in the
data input sequence ALE and CLE are latched HIGH, and
CAD is met,
t
WPST, the bus enters bus idle mode and
t
Micron Confidential and Proprietary
CAD starts, the host can disable the target if desired.
8Gb Asychronous/Synchronous NAND Flash Memory
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSS, data is written from DQ[7:0] to the
t
t
t
DSH and
DSH and
CAD begins on the next rising edge
t
WPST.
t
t
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DSS,
DSS,
Bus Operation
Advance