MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 35

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MT29F8G08ABABAWP:B

Manufacturer Part Number
MT29F8G08ABABAWP:B
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08ABABAWP:B

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Vcc Power Cycling
Figure 25:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Supply Voltage
Power Cycle
Command input prohibited
V
V
CC
CC
Notes:
Q (MIN)
(MIN)
1. Ramp V
2. Ramp V
3. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to any
4. If not monitoring R/B#, the host must wait at least 100µs after Vcc/V
5. All of the targets on the device power on with the asynchronous interface active. Each
6. The RESET (FFh) command must be the first command issued to all targets (CE#s)
7. The device is now initialized and ready for normal operation.
High-Speed NAND Flash devices are designed to prevent data corruption during power
transitions. Vcc is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping V
procedure to initialize the device:
At power-down, V
LOW.
1. Vcc is exaggerated over VccQ in this figure for illustrative purposes.
3b. 10µs has elapsed since V
3a. 50µs has elapsed since the beginning the V
time.
target (see Figure 26 on page 36). The R/B# signal becomes valid when:
MIN.
NAND Flash LUN draws less than an average of 10mA (IST) measured over intervals
of 1ms until the RESET (FFh) command is issued.
after the NAND Flash device is powered on. Each target will be busy for a maximum of
t
polling R/B# or issuing the READ STATUS (70h) command to poll the status register.
POR after a RESET command is issued. The RESET busy time can be monitored by
CC
CC
Q to MIN-MAX no sooner than V
to 2.7–3.6V.
Micron Confidential and Proprietary
V
V
CC
CC
CC
8Gb Asychronous/Synchronous NAND Flash Memory
Q
Q must go LOW, either before, or simultaneously with, V
35
CC
/V
CC
Q reached MIN.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command input prohibited
CC
. V
CC
CC
ramp, and
Q and V
CC
and V
CC
©2008 Micron Technology, Inc. All rights reserved.
CC
may ramp at the same
Vcc Power Cycling
Q, use the following
Time
CC
Q reaches
CC
going
Advance

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