MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 61

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MT29F8G08ABABAWP:B

Manufacturer Part Number
MT29F8G08ABABAWP:B
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08ABABAWP:B

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Figure 40:
CHANGE ROW ADDRESS (85h)
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
I/O[7:0] (DQ[7:0])
CHANGE WRITE COLUMN (85h) Operation
Notes:
Cycle type
As defined for PAGE
(CACHE) PROGRAM
SR[6]
1. When used with these commands, the LUN address and plane-select bits must be
The CHANGE ROW ADDRESS (85h) command changes the row address (block and
page) where the cache register contents will be programmed in the NAND Flash array. It
also changes the column address of the selected cache register and enables data input
on the specified LUN. This command is accepted by the selected LUN when it is ready
(RDY = 1; ARDY = 1). It is also accepted by the selected LUN during cache programming
operations (RDY = 1; ARDY = 0).
Writing 85h to the command register, then writing two column address cycles and three
row address cycles, updates the page and block destination of the selected plane for the
addressed LUN, and puts the cache register into data input mode. After the fifth address
cycle is issued, the host must wait at least
stays in data-input mode until another valid command is issued. Though data-input
mode is enabled, data input from the host is optional. Data input begins at the column
address specified.
The CHANGE ROW ADDRESS (85h) command is supported prior to the final command
cycle (10h, 11h, 15h) of the following commands
The CHANGE ROW ADDRESS (85h) command enables the host to modify the original
page and block address for the data in the cache register to a new page and block
address.
The CHANGE ROW ADDRESS (85h) command can be used with the CHANGE READ
COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) commands to
read and modify cache register contents in small sections prior to programming cache
register contents to the NAND Flash array. This capability can reduce the amount of
buffer memory used in the host controller.
To modify the cache register contents in small sections, first issue a PAGE READ (00h-
30h) or COPYBACK READ (00h-35h) operation. When data output is enabled, the host
can output a portion of the cache register contents. To modify the cache register
contents, issue the 85h command, the column and row addresses, and input the new
– PROGRAM PAGE (80h-10h)
– PROGRAM PAGE MULTI-PLANE (80h-11h)
– PROGRAM PAGE CACHE (80h-15h)
– COPYBACK PROGRAM (85h-10h)
– COPYBACK PROGRAM MULTI-PLANE (85h-11h).
identical to the LUN address and plane-select bits originally specified.
D
Dn
IN
Dn + 1
D
IN
Micron Confidential and Proprietary
Command
8Gb Asychronous/Synchronous NAND Flash Memory
85h
Address
C1
61
Address
C2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CCS before inputting data. The selected LUN
t CCS
1
:
D
Dk
IN
Command Definitions
Dk + 1
As defined for PAGE
D
(CACHE) PROGRAM
IN
©2008 Micron Technology, Inc. All rights reserved.
Dk + 2
D
IN
Advance

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