MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 69

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

READ PAGE MULTI-PLANE (00h–32h)
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Note:
Note:
1. The READ PAGE MULTI-PLANE (00h-32) is issued. The column address in the address
2. R/B# goes LOW and the LUN is busy (RDY = 0, ARDY = 0) for
3. The READ PAGE CACHE RANDOM (00h-31h) is issued. The column address in the
4. R/B# goes LOW and the LUN is busy (RDY = 0, ARDY = 0) for
1. 00h is written to the command register.
2. Five address cycles are written to the address register.
The second option is to issue the READ PAGE MULTI-PLANE (00h-32h) command
followed by the READ PAGE CACHE RANDOM (00h-31h) command. By using READ
PAGE MULTI-PLANE (00h-32h) command and the READ PAGE CACHE RANDOM (00h-
31h) random page addresses within the NAND device can be selected instead of just the
next sequential page address as with the READ PAGE CACHE SEQUENTIAL (31h)
command. The column address with the READ PAGE MULTI-PLANE is ignored, data will
come from byte 0 of subsequent pages read.
The following shows this sequence:
After R/B# goes HIGH and the LUN reports in the status register RDY = 1 and ARDY = 0,
that signals that the internal array read is ongoing and the cache register is ready to
output data from the previous read operation. The SELECT CACHE REGISTER (06h-E0h)
command is required prior to outputting data. After the SELECT CACHE REGISTER
(06h-E0h) command is issued, the CHANGE READ COLUMN (05h-E0h) command can
also be issued.
After issuing the last page address to be read, issue the READ PAGE CACHE LAST (3Fh)
to finish the cache reading operation. Data output is similar to the previous cache read
operations, requiring the SELECT CACHE REGISTER (06h-E0h) command to be issued
first.
See “Multi-Plane Addressing” on page 86 for additional multi-plane addressing require-
ments
The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data
from the NAND flash array to its cache register. This command can be issued one or
more times. Each time a new plane address is specified, that plane is also queued for
data transfer. The READ PAGE (00h-30h) command is issued to select the final plane and
to begin the read operation for all previously queued planes. All queued planes will
transfer data from the NAND Flash array to their cache registers.
This command is issued in the following sequence:
To enable data output in the other cache register or change the column address, the
SELECT CACHE REGISTER (06h-E0h) command can be issued. Also, to change the
column address within the currently selected plane (after the SELECT CACHE REGIS-
TER (06h-E0h) command is issued), the CHANGE READ COLUMN (05h-E0h) com-
mand can be issued.
specified is ignored.
address specified is ignored.
To enable data output in the other cache register or change the column address, the
SELECT CACHE REGISTER (06h-E0h) command can be issued. Also, to change the
column address within the currently selected plane (after the SELECT CACHE REGIS-
TER (06h-E0h) command is issued), the CHANGE READ COLUMN (05h-E0h) com-
mand can be issued.
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8Gb Asychronous/Synchronous NAND Flash Memory
69
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Command Definitions
©2008 Micron Technology, Inc. All rights reserved.
t
t
DBSY.
RCBSY.
Advance