MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 72

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

PROGRAM PAGE (80h–10h)
Figure 46:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Cycle type
(DQ[7:0])
I/O[7:0]
RDY
Command
80h
PROGRAM PAGE (80h–10h) Operation
Address
Note:
C1
Address
C2
1. 80h is written to the command register.
2. A page is input to the cache register and moved to the NAND Flash array at the block
3. Five address cycles containing the column address and row address are written to the
4. The data input cycle begins. Serial data is input, beginning at the specified column
5. When the data input cycle has completed, 10h is written to the command register.
6. The selected LUN goes busy (RDY = 0, ARDY = 0) for
7. If a multi-plane program operation is being performed, the PROGRAM PAGE (80h-
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache
register, and moves the data from the cache register to the specified block and page
address in the array of the selected LUN. This command is accepted by the LUN when it
is ready (RDY = 1, ARDY = 1). It is also accepted by the LUN when it is busy with a
PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
This command is issued in the following sequence:
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) may be used. When the LUN is
ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.
In devices that have more than one LUN per target, during and following multi-LUN
operations, the SELECT LUN WITH STATUS (78h) command must be used to select only
one LUN for status output. Use of the READ STATUS (70h) command could cause more
than one LUN to respond, resulting in bus contention.
Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE
(80h-11h) command, issuing 80h to the command register clears all of the cache reg-
ister contents on the selected target.
and page address specified.
address register.
address. At any time during the data input cycle, the CHANGE READ COLUMN (05h)
and CHANGE ROW ADDRESS (85h) commands can be issued.
10h) command is written to the command register as the final command. It is pre-
ceded by one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands. Data is
transferred from the cache registers for all of the addressed planes to the NAND Flash
array. The host should check the status of the operation by using the status operations
(70h, 78h). See“Multi-Plane Addressing” on page 86 for multi-plane addressing
requirements.
Address
R1
Address
R2
Micron Confidential and Proprietary
Address
R3
8Gb Asychronous/Synchronous NAND Flash Memory
t ADL
D
72
D0
IN
D
D1
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
…
IN
D
Dn
IN
Command
t
PROG as data is transferred.
10h
Command Definitions
t WB
©2008 Micron Technology, Inc. All rights reserved.
t PROG
Command
70h
Advance
Status
D
OUT