MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 73

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

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PROGRAM PAGE CACHE (80h–15h)
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m61a_async_sync_nand.fm - Rev. A 2/09 EN
Note:
1. 80h is written to the command register.
2. Five address cycles containing the column address and row address are written [to the
3. The data input cycles follow. Serial data is input, beginning at the specified column
4. When the data input cycle has completed, 15h is written to the command register.
5. The selected LUN goes busy (RDY = 0, ARDY = 0) for
6. If, after
7. The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the
selected LUN. After the data is copied to the data register, the cache register is available
for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the LUN
when it is ready (RDY = 1, ARDY = 1). It is also accepted by the LUN when busy with a
PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
This command is issued in the following sequence to input a page to the cache register
and move it to the NAND array at the block and page address specified:
Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE
(80h-11h) command, issuing 80h to the command register clears all of the cache reg-
ister’s contents on the selected target.
address register.
address. At any time during the data input cycle, the CHANGE READ COLUMN (85h)
and CHANGE ROW ADDRESS (85h) commands can be issued.
time to become available from a previous program cache operation; to copy data
from the cache register to the data register; then begin moving the data register con-
tents to the specified page and block address.
To determine the progress of
alternatively, the status operations (70h, 78h) can be used. When the LUN’s status
shows that it is busy with a program cache operation (RDY = 1, ARDY = 0), the host
should check the status of the FAILC bit to see if a previous cache operation was suc-
cessful.
without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor
ARDY until it is “1.” The host should then check the status of the FAIL and FAILC bits.
In devices with more than one LUN per target, during and following multi-LUN oper-
ations, the SELECT LUN WITH STATUS (78h) command must be used to select only
one LUN for status output. Use of the READ STATUS (70h) command could cause
more than one LUN to respond, resulting in bus contention.
multi-plane program cache operation. It is preceded by one or more PROGRAM PAGE
MULTI-PLANE (80h-11h) commands. Data for all of the addressed planes is trans-
ferred from the cache registers to the corresponding data registers, then moved to the
NAND Flash array. The host should check the status of the operation by using the sta-
tus operations (70h, 78h). See“Multi-Plane Addressing” on page 86 for multi-plane
addressing requirements.
t
CBSY, the host wants to wait for the program cache operation to complete,
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8Gb Asychronous/Synchronous NAND Flash Memory
73
t
CBSY, the host can monitor the target's R/B# signal or,
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t
CBSY to give the data register
Command Definitions
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