MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 75

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MT29F8G08ABABAWP:B

Manufacturer Part Number
MT29F8G08ABABAWP:B
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT29F8G08ABABAWP:B

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Figure 49:
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Cycle type
(DQ[7:0])
I/O[7:0]
RDY
Command
PROGRAM PAGE MULTI-PLANE (80h–11h) Operation
80h
Address
C1
planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM PAGE
CACHE (80h-15h) command. All of the queued planes will move the data to the NAND
Flash array. This command is accepted by the LUN when it is ready (RDY = 1).
To input a page to the cache register and queue it to be moved to the NAND Flash array
at the block and page address specified, write 80h to the command register. Unless this
command has been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h)
command, issuing the 80h to the command register clears all of the cache registers'
contents on the selected target. Write five address cycles containing the column address
and row address; data input cycles follow. Serial data is input beginning at the column
address specified. At any time during the data input cycle, the CHANGE READ COLUMN
(85h) and CHANGE ROW ADDRESS (85h) commands can be issued. When data input is
complete, write 11h to the command register. The selected LUN will go busy (RDY = 0 ,
ARDY = 0) for
To determine the progress of
alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows
that it is ready (RDY = 1), additional PROGRAM PAGE MULTI-PLANE (80h-11h)
commands can be issued to queue additional planes for data transfer. Alternatively, the
PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be
issued.
When the PROGRAM PAGE (80h-10h) command is used as the final command of a
multi-plane program operation, data is transferred from the cache registers to the NAND
Flash array for all of the addressed planes during
(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the
planes to verify that programming completed successfully.
When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command of
a MULTI-PLANE PROGRAM CACHE operation, data is transferred from the cache regis-
ters to the data registers after the previous array operations finish. The data is then
moved from the data registers to the NAND Flash array for all of the addressed planes.
This occurs during
for each of the planes from the previous program cache operation, if any, to verify that
programming completed successfully.
For the PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and
PROGRAM PAGE CACHE (80h-15h) commands, See “Multi-Plane Addressing” on
page 86 for multi-plane addressing requirements.
Address
C2
Address
R1
Micron Confidential and Proprietary
t
DBSY.
Address
R2
t
8Gb Asychronous/Synchronous NAND Flash Memory
CBSY. After
Address
R3
t
75
DBSY, the host can monitor the target's R/B# signal, or
t ADL
t
CBSY, the host should check the status of the FAILC bit
D
D0
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
IN
t
PROG. When the LUN is ready
D
Dn
IN
Command
11h
Command Definitions
t WB t DBSY
©2008 Micron Technology, Inc. All rights reserved.
Command
80h
Address
Advance
...

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