MT29F8G08ABABAWP:B Micron Technology Inc, MT29F8G08ABABAWP:B Datasheet - Page 86

• Manufacturer Part Number: MT29F8G08ABABAWP:B
• Manufacturer: Micron Technology Inc

Specifications of MT29F8G08ABABAWP:B

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Multi-Plane Operations
Multi-Plane Addressing
Multi-LUN Operations
PDF: 09005aef8386131b / Source: 09005aef838cad98
m61a_async_sync_nand.fm - Rev. A 2/09 EN
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane
contains a cache register and a data register independent of the other planes. The planes
are addressed via the low-order block address bits. Specific details are provided in Figure
8 and Table 2 on page 13.
Multi-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Multi-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing MULTI-PLANE PROGRAM or ERASE operations, use the READ STATUS
(70h) command and check whether the previous operation(s) failed. If the READ
STATUS (70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1),
use the SELECT LUN WITH STATUS (78h) command—time for each plane—to deter-
mine which plane operation failed.
Multi-plane commands require multiple 5-cycle addresses, one address per operational
plane. For a given multi-plane operation, these addresses are subject to the following
requirements:
• The LUN address bit(s) must be identical for all of the issued addresses.
• The plane select bit, BA[7], must be different for each issued address.
• The page address bits, PA[6:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following MULTI-PLANE PROGRAM
PAGE and ERASE BLOCK operations on a single LUN.
In devices that have more than one LUN per target, it is possible to improve perfor-
mance by interleaving operations between the LUNs. A multi-LUN operation is one that
is issued to an idle LUN (RDY = 1) while another LUN is busy (RDY = 0).
Multi-LUN operations are prohibited following RESET (FFh, FCh), identification (90h,
ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of the LUNs on
the target.
During a multi-LUN operation, there are two methods to determine operation comple-
tion. The R/B# signal indicates when all of the LUNs have finished their operations.
R/B# remains LOW while any LUN is busy. When R/B# goes HIGH, all of the LUNs are
idle and the operations are complete. Alternatively, the SELECT LUN WITH STATUS
(78h) command can report the status of each LUN individually.
If a LUN is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h), then
the LUN is able to accept the data for another cache operation when status register bit 6
is "1." All operations, including cache operations, are complete on a die when status
register bit 5 is "1."
Micron Confidential and Proprietary
8Gb Asychronous/Synchronous NAND Flash Memory
86
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Multi-Plane Operations
©2008 Micron Technology, Inc. All rights reserved.
Advance