S25FL016A0LMFI011 Spansion Inc., S25FL016A0LMFI011 Datasheet - Page 13

• Manufacturer Part Number: S25FL016A0LMFI011
• Manufacturer: Spansion Inc.

Specifications of S25FL016A0LMFI011

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 10ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Compliant

7.6
7.7
February 27, 2009 S25FL016A_00_C4
Data Protection Modes
Hold Mode (HOLD#)
Spansion SPI Flash memory devices provide the following data protection methods:
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of
SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
BP2
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased.
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
0
0
0
0
1
1
1
1
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Block Protect Bits
Status Register
BP1
0
0
1
1
0
0
1
1
BP0
Figure
0
1
0
1
0
1
0
1
D a t a
7.1.
1F0000h–1FFFFFh
1E0000h–1FFFFFh
1C0000h–1FFFFFh
180000h–1FFFFFh
100000h–1FFFFFh
000000h–1FFFFFh
000000h–1FFFFFh
Address Range
Protected
None
Table 7.1 S25FL016A Protected Area Sizes
S h e e t
S25FL016A
(16) SA31:SA16
(2) SA31:SA30
(4) SA31:SA28
(8) SA31:SA24
(32) SA31:SA0
(32) SA31:SA0
Protected
(1) SA31
Sectors
(0)
Memory Array
000000h–1EFFFFh
000000h–1DFFFFh
000000h–1BFFFFh
000000h–1FFFFFh
000000h–17FFFFh
000000h–0FFFFFh
Address Range
Unprotected
Table 7.1
None
None
Figure
shows the sizes and address
7.1, standard use). If the
Unprotected
SA31:SA0
SA30:SA0
SA29:SA0
SA27:SA0
SA23:SA0
SA15:SA0
Sectors
None
None
Total Memory
Protected
Portion of
Area
1/32
1/16
1/8
1/4
1/2
All
All
0
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