S25FL016A0LMFI011

Manufacturer Part NumberS25FL016A0LMFI011
ManufacturerSpansion Inc.
S25FL016A0LMFI011 datasheet
 


Specifications of S25FL016A0LMFI011

Cell TypeNORDensity16Mb
Access Time (max)10nsInterface TypeSerial (SPI)
Boot TypeNot RequiredAddress Bus1b
Operating Supply Voltage (typ)3/3.3VOperating Temp Range-40C to 85C
Package TypeSOIC WProgram/erase Volt (typ)2.7 to 3.6V
Sync/asyncSynchronousOperating Temperature ClassificationIndustrial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (max)3.6V
Word Size8bNumber Of Words2M
Supply Current19mAMountingSurface Mount
Pin Count8Lead Free Status / RoHS StatusCompliant
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7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased.
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
Status Register
Block Protect Bits
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of
SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
Figure
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
February 27, 2009 S25FL016A_00_C4
D a t a
S h e e t
Table 7.1 S25FL016A Protected Area Sizes
Memory Array
Protected
Protected
Address Range
Sectors
Address Range
None
(0)
000000h–1FFFFFh
1F0000h–1FFFFFh
(1) SA31
000000h–1EFFFFh
1E0000h–1FFFFFh
(2) SA31:SA30
000000h–1DFFFFh
1C0000h–1FFFFFh
(4) SA31:SA28
000000h–1BFFFFh
180000h–1FFFFFh
(8) SA31:SA24
000000h–17FFFFh
100000h–1FFFFFh
(16) SA31:SA16
000000h–0FFFFFh
000000h–1FFFFFh
(32) SA31:SA0
000000h–1FFFFFh
(32) SA31:SA0
7.1.
S25FL016A
Table 7.1
shows the sizes and address
Protected
Portion of
Unprotected
Unprotected
Total Memory
Sectors
Area
SA31:SA0
0
SA30:SA0
1/32
SA29:SA0
1/16
SA27:SA0
1/8
SA23:SA0
1/4
SA15:SA0
1/2
None
None
All
None
None
All
Figure
7.1, standard use). If the
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