S25FL064A0LMFI001 Spansion Inc., S25FL064A0LMFI001 Datasheet
S25FL064A0LMFI001
Specifications of S25FL064A0LMFI001
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S25FL064A0LMFI001 Summary of contents
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... Availability of this document is retained for reference and historical purposes only. Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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... Publication Number S25FL064A_00 This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com- binations offered may occur ...
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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 2.1 16-pin Plastic Small Outline Package (SO ...
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Tables Table 5.1 S25FL064A Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Diagram SRAM Logic 2. Connection Diagrams Array - L RD DATA PATH IO Figure 2.1 16-pin Plastic Small Outline Package (SO) 16 HOLD VCC 3 ...
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Input/Output Descriptions Signal I/O SO Output SI Input SCK Input CS# Input HOLD# Input W# Input V Input CC GND Input 4. Logic Symbol February 27, 2009 S25FL064A_00_C4 Description Signal ...
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... DEVICE FAMILY S25FL TM Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL064A Valid Combinations Table S25FL064A Valid Combinations Package & Speed Option Temperature MAI, MFI, 0L NAI, NFI S25FL064A PACKING TYPE (Note Tray ...
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... Spansion SPI Modes A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode 3) Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes ...
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Device Operations All Spansion SPI devices (S25FL-A) accept and output data in bytes (8 bits at a time). 7.1 Byte or Page Programming Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program ...
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... Data Protection Modes Spansion SPI Flash memory devices provide the following data protection methods: The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following commands: – ...
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... Each page or byte can be individually programmed (bits are changed from 1 to 0). The data is erased (bits are changed from sector- or device-wide basis using the commands. address for each sector. The complete set of sectors comprises the memory array of the Flash device. Each Device has 8,388,608 ...
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Sector Address Range SA127 7F0000h 7FFFFFh SA126 7E0000h 7EFFFFh SA125 7D0000h 7DFFFFh SA124 7C0000h 7CFFFFh SA123 7B0000h 7BFFFFh SA122 7A0000h 7AFFFFh SA121 790000h 79FFFFh SA120 780000h 78FFFFh SA119 770000h 77FFFFh SA118 760000h 76FFFFh SA117 750000h 75FFFFh SA116 740000h 74FFFFh SA115 ...
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Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven low, the device accepts ...
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Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ command reads data from the memory array at the frequency (f input, with a maximum speed of 50 MHz. The host system must first select the device by driving CS# ...
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Read Identification (RDID) The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device identification, to the host system. JEDEC assigns the manufacturer identification byte; for Spansion devices it is 01h. The device manufacturer assigns ...
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Write Enable (WREN) The Write Enable (WREN) command (see enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set prior to every Page Program (PP), Erase (SE or BE) and ...
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Read Status Register (RDSR) The Read Status Register (RDSR) command outputs the state of the Status Register bits. the status register bits and their functions. The RDSR command may be written at any time, even while a program, erase, ...
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... The WRSR command cannot change the state of the Write Enable Latch (bit 1). The WREN command must be used for that purpose. Bit status bit controlled internally by the Flash device. Bits 6 and 5 are always read as 0 and have no user significance. The WRSR command also controls the value of the Status Register Write Disable (SRWD) bit. The SRWD bit and W# together place the device in the Hardware Protected Mode (HPM) ...
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W# SRWD Signal Bit Mode 1 1 Software 1 0 Protected (SPM Hardware 0 1 Protected (HPM) Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in ...
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Page Program (PP) The Page Program (PP) command changes specified bytes in the memory array (from only). A WREN command is required prior to writing the PP command. The host system must drive CS# low, and ...
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Sector Erase (SE) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the PP command. The host system must drive CS# ...
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Bulk Erase (BE) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the PP command. The host system must drive CS# low, and ...
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Deep Power Down (DP) The Deep Power Down (DP) command provides the lowest power consumption mode of the device intended for periods when the device is not in active use, and ignores all commands except for the ...
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Release from Deep Power Down (RES) The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down mode. When the device is in the Deep Power Down mode, all commands except RES are ...
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Release from Deep Power Down and Read Electronic Signature (RES) The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.13 and Table 9.4 on page 28 Signature is not to be ...
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Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied and must not be driven low to select the device until V CC (see Figure 10.1 and At ...
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Absolute Maximum Ratings Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. These are stress ratings only and device operation at these or any other conditions beyond ...
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DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in on page 31, when relying on the quoted ...
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AC Characteristics Symbol (Notes) F SCK Clock Frequency READ command SCK SCK Clock Frequency for: F SCK FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR t Clock Rise Time (Slew Rate) CRT t Clock Fall Time (Slew ...
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CS# t CSH SCK SI Hi-Z SO CS# SCK CS# SCK SO SI HOLD# February 27, 2009 S25FL064A_00_C4 Figure 16.1 SPI Mode 0 (0,0) Input Timing t CSS ...
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Figure 16.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 W# CS# SCK SI Hi WPS S25FL064A t WPH S25FL064A_00_C4 February 27, 2009 ...
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... THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE 0.48 OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF 0.33 MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP 0.30 AND BOTTOM OF THE PLASTIC BODY. 10.30 BSC 5 ...
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Revision History Section Revision A (April 26, 2005) Global Initial release. Revision B0 (April 18, 2006) Changed document status from Advance Information to Preliminary. Changed title from family of Global devices to specific device. AC Characteristics table Updated t ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2005-2009 Spansion Inc. All rights reserved. Spansion ™ ™ ...