MT45W1MW16PDGA-70 IT Micron Technology Inc, MT45W1MW16PDGA-70 IT Datasheet
MT45W1MW16PDGA-70 IT
Specifications of MT45W1MW16PDGA-70 IT
Related parts for MT45W1MW16PDGA-70 IT
MT45W1MW16PDGA-70 IT Summary of contents
Page 1
... DQ1 DQ2 V Q DQ11 A17 A7 DQ3 DQ12 NC A16 DQ4 A15 DQ14 DQ13 A14 DQ5 DQ6 A13 DQ15 A19 A12 WE# DQ7 A18 A8 A9 A10 A11 NC Top View (Ball Down) Part Number Example: MT45W1MW16PDGA-70WT ©2005 Micron Technology, Inc. All rights reserved. Features CC SS ...
Page 2
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
List of Figures Figure 1: Ball Assignment – 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of Tables Table 1: VFBGA Ball Descriptions ...
Page 5
General Description Micron oped for low-power, portable applications. The MT45W1MW16PD is a 16Mb DRAM core device organized as 1 Meg x 16 bits. These devices include the industry-standard, asyn- chronous memory interface found on other low-power SRAM or pseudo-SRAM offer- ...
Page 6
Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Ball Assignment Symbol Type G2, H1, D3, E4, A[19:0] Input F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 ZZ# Input B5 CE# Input ...
Page 7
Bus Operations Table 2: Bus Operations Mode Power Standby Standby Active Read Write Active No operation Idle PAR Partial-array refresh Deep power-down DPD Active Load configuration register Notes: 1. When LB# and UB# are in select mode (LOW), DQ[15:0] are ...
Page 8
Part Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart -70 Micron Technology Product Family 45 = PSRAM/CellularRAM Memory ...
Page 9
Functional Description In general, the MT45W1MW16PD device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W1MW16PD contains a 16,777,216-bit DRAM core organized as 1,048,576 addresses by 16 bits. These devices include the ...
Page 10
Figure 5: READ Operation CE# OE# WE# ADDRESS DATA LB#/UB# Figure 6: WRITE Operation CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory ADDRESS VALID DATA ...
Page 11
Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous read access is per- formed, then adjacent addresses can be quickly read by simply changing the low-order address. ...
Page 12
Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to per- form the DRAM refresh operation on the full array. Standby operation occurs when CE# and ZZ# are HIGH. The device will ...
Page 13
Figure 8: Software Access PAR Functionality NO Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become ...
Page 14
Configuration Register Operation The configuration register (CR) defines how the CellularRAM device performs its trans- parent self refresh. Altering the refresh parameters can dramatically reduce current con- sumption during standby mode. Page mode control is also embedded into the CR. ...
Page 15
Figure 10: Software Access Load Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Note: If the data at the falling edge of WE# is not 0000h possible that the data stored at the highest memory location will be ...
Page 16
Figure 12: Configuration Register Bit Mapping A[19:8] 19–8 RESERVED All must be set to "0" CR[7] Page Mode Enable/Disable 0 Page Mode Disabled (default) 1 Page Mode Enabled CR[6] CR[5] Maximum Case Temp +85˚ Internal sensor ...
Page 17
The TCR bits also allow for adequate fixed-rate refresh at three different temperature thresholds (+15°C, +45°C, and +85°C). The setting selected must be for a temperature higher than the case temperature of the CellularRAM device. If the case temperature is ...
Page 18
Electrical Characteristics Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
Page 19
Table 5: Electrical Characteristics and Operating Conditions Wireless temperature Description Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage I Output low voltage V Input leakage current IN OE Output leakage current Chip ...
Page 20
Maximum and Typical Standby Currents Table 6 and Figure 13 refer to the maximum and typical standby currents for the MT45W1MW16PD device. The typical values shown in Figure 13 are measured with the default on-chip temperature sensor control enabled. The ...
Page 21
Table 7: Deep Power-Down Specifications and Conditions Description Deep power-down Table 8: Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. Figure 14: AC ...
Page 22
Table 9: READ Cycle Timing Requirements Parameter Address access time Page access time LB#/UB# access time LB#/UB# disable to High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time Chip disable to High-Z output Chip ...
Page 23
Table 10: WRITE Cycle Timing Requirements Parameter Address setup time Address valid to end of write Byte select to end of write CE# HIGH time during write Chip enable to end of write Data hold from write time Data write ...
Page 24
Timing Diagrams Figure 16: Power-Up Initialization Period Vcc, VccQ = 1.7V Table 13: Initialization Timing Parameters Parameter Initialization period (required before normal operations) Figure 17: Load Configuration Register ADDRESS CE# LB#/UB# WE# OE# ZZ# Figure 18: Deep Power-Down – Entry/Exit ...
Page 25
Figure 19: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Figure 20: Page Mode READ Operation (WE ADDRESS A[19:4] ADDRESS A[3:0] LB#/UB# DATA-OUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page ...
Page 26
Figure 21: WRITE Cycle (WE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT Figure 22: WRITE Cycle (CE# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory t ...
Page 27
Figure 23: WRITE Cycle (LB#/UB# Control) ADDRESS LB#/UB# WE# DATA-IN DATA-OUT PDF: 09005aef81cadc83/Source:09005aef81c6edb4 16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN 16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory t WC ADDRESS VALID CE ...
Page 28
Package Dimensions Figure 24: 48-Ball VFBGA 0.70 ±0.05 SEATING PLANE A 0.10 A 48X Ø0.37 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PRE-REFLOW BALL DIAMETER IS 0. 0.30 SMD BALL PAD. BALL A6 5.25 2.625 1.875 6.00 ±0.10 ...
Page 29
Revision History Rev. F, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...