MT45W1MW16BDGB-708 WT Micron Technology Inc, MT45W1MW16BDGB-708 WT Datasheet - Page 18

• Manufacturer Part Number: MT45W1MW16BDGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BDGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Low-Power Operation
Standby Mode Operation
Temperature-Compensated Refresh
Partial-Array Refresh
Deep Power-Down Operation
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE oper-
ation or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
Temperature-compensated refresh (TCR) allows for adequate refresh at different
temperatures. This CellularRAM device includes an on-chip temperature sensor. When
the sensor is enabled, it continually adjusts the refresh rate according to the operating
temperature. The on-chip sensor is enabled by default.
Three fixed refresh rates are also available, corresponding to temperature thresholds of
+15°C, +45°C, and +85°C. The setting selected must be for a temperature higher than the
case temperature of the CellularRAM device. If the case temperature is +35°C, the system
can minimize self refresh current consumption by selecting the +45°C setting. The +15°C
setting would result in inadequate refreshing and cause data corruption.
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of
these partitions can start at either the beginning or the end of the address map (see
Table 6 on page 28). READ and WRITE operations to address ranges receiving refresh will
not be affected. Data stored in addresses not receiving refresh will become corrupted.
When re-enabling additional portions of the array, the new portions are available imme-
diately upon writing to the RCR.
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled by rewriting the RCR, the CellularRAM device will require 150µs to perform
an initialization procedure before normal operations can resume. During this 150µs
period, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access
sequence; the RCR should be accessed using CRE instead.
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2005 Micron Technology, Inc. All rights reserved.