MT45W1MW16BDGB-708 WT Micron Technology Inc, MT45W1MW16BDGB-708 WT Datasheet - Page 27

• Manufacturer Part Number: MT45W1MW16BDGB-708 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BDGB-708 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Refresh Configuration Register
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
Figure 22:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
RCR[6] RCR[5]
RCR[19]
RCR[7]
1
0
1
0
0
1
0
1
Register
Select
Refresh Configuration Register Mapping
19
All must be set to "0"
A19
Select RCR
Select BCR
1
0
1
0
Register Select
Page Mode Disabled (default)
Page Mode Enable
RESERVED
Page Mode Enable/Disable
+15°C
Internal sensor (default)
+45°C
+85°C
Maximum Case Temp.
18–8
A[18:8]
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce
current consumption during standby mode. Page mode control is also embedded into
the RCR. Figure 22 describes the control bits used in the RCR. At power-up, the RCR is set
to 0010h.
The RCR is accessed using CRE and A[19] LOW; or through the configuration register
software access sequence with DQ = 0000h on the third cycle (see “Configuration Regis-
ters” on page 19.)
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map (see Table 6 on
page 28).
PAGE
7
A7
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
6
TCR
A6
5
A5
RCR[4]
DPD
0
1
4
A4
Must be set to "0"
27
RESERVED
RCR[2]
DPD Enable
DPD Disable (default)
0
0
0
0
1
1
1
1
Deep Power-Down
3
A3
RCR[1]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
1
1
0
1
0
0
0
2
A2
RCR[0]
0
1
0
1
1
0
0
1
PAR
None of array
Top 1/8 array
Bottom 1/4 array
Bottom 1/8 array
Top 1/2 array
Top 1/4 array
Full array (default)
Bottom 1/2 array
1
A1
Refresh Coverage
Configuration Registers
©2005 Micron Technology, Inc. All rights reserved.
0
A0
Address Bus