MT45W1MW16BDGB-708 AT Micron Technology Inc, MT45W1MW16BDGB-708 AT Datasheet - Page 49

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MT45W1MW16BDGB-708 AT

Manufacturer Part Number
MT45W1MW16BDGB-708 AT
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT45W1MW16BDGB-708 AT

Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Figure 39:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
DQ[15:0]
LB#/UB#
A[19:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
IH
IH
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
IL
IL
IL
Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row
Condition
Notes:
t CLK
VALID INPUT
t SP
1. Non-default BCR settings for continuous burst WRITE, BCR[8] = 0; WAIT active LOW; WAIT
2. CE# must not remain LOW longer than
3. WAIT asserts for anywhere from LC to 2LC cycles. LC = latency code (BCR[13:11]).
4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write
(A[6:0] = 7Fh)
End of row
asserted during delay. Do not cross row boundaries with fixed latency.
the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that
the start-of-row data is input just before (as shown), or just after WAIT asserts. This differ-
ence in behavior will not be noticed by controllers that monitor WAIT, or that use WAIT to
abort on the start-of-row input cycle.
t HD
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
VALID INPUT
Start of row
(A[6:0] = 00h)
(NOTE 4)
t KHTL
49
Note 4
Note 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CEM.
t KHTL
©2005 Micron Technology, Inc. All rights reserved.
VALID INPUT
Timing Diagrams
DON’T CARE
VALID INPUT

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