MT45W1MW16BDGB-708 AT Micron Technology Inc, MT45W1MW16BDGB-708 AT Datasheet - Page 8

• Manufacturer Part Number: MT45W1MW16BDGB-708 AT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BDGB-708 AT

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Bus Operations
Table 2:
Table 3:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
Mode
Mode
Read
Write
Standby
No operation
Configuration
Register
DPD
Async read
Async write
Standby
No operation
Initial burst
read
Initial burst
write
Burst
continue
Burst suspend
Configuration
register
DPD
Bus Operations – Asynchronous Mode
Bus Operations – Burst Mode
power-down
power-down
Notes:
Standby
Power
Active
Active
Active
Active
Active
Active
Active
Standby
Deep
Power
Active
Active
Active
Idle
Deep
Idle
1. CLK must be LOW during async read and async write modes, and to achieve standby power
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
6. V
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend.
select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are
affected.
isolated from any external influence.
rent.
IN
CLK
= V
X
CLK
L
L
L
L
L
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
L
L
L
L
L
L
1
CC
1
Q or 0V; all device balls must be static (unswitched) in order to achieve standby cur-
ADV#
ADV#
X
X
H
X
X
L
L
L
L
L
X
X
X
L
L
L
CE#
H
H
L
L
CE#
L
L
L
L
L
L
H
H
L
L
L
L
OE#
8
OE#
X
X
X
X
H
X
H
H
X
L
X
X
H
X
X
L
WE#
WE#
H
X
X
H
X
X
X
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
X
X
X
L
L
CRE
CRE
X
H
X
L
L
L
L
L
L
L
H
X
L
L
L
L
LB#/
UB#
LB#/
UB#
X
X
X
X
X
X
L
L
L
L
X
X
X
X
L
L
WAIT
High-Z
High-Z
WAIT
High-Z
High-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
Low-Z
©2005 Micron Technology, Inc. All rights reserved.
2
2
Bus Operations
DQ[15:0]
DQ[15:0]
Data-In or
Data-Out
Data-Out
Data-Out
Data-In
Data-In
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
X
X
X
3
3
Notes
Notes
5, 6
4, 6
4, 8
4, 8
4, 8
4, 8
5, 6
4, 6
4
4
8
7
4
4
7