MT45W1MW16BDGB-708 IT TR Micron Technology Inc, MT45W1MW16BDGB-708 IT TR Datasheet - Page 23

• Manufacturer Part Number: MT45W1MW16BDGB-708 IT TR
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16BDGB-708 IT TR

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Bus Configuration Register
Figure 17:
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
Register
Select
BCR[19]
19
A19
Must be set to "0"
0
1
Reserved
A[18:16]
18–16
Select RCR
Select BCR
BCR[15]
Bus Configuration Register Definition
0
1
Operating
Mode
BCR[13]
15
A15
Register Select
0
0
0
0
1
1
1
1
Must be set to "0"
BCR[10]
BCR[8]
Asynchronous access mode (default)
Synchronous burst access mode
0
1
0
1
Reserved
Note:
BCR[12] BCR[11]
14
0
0
1
1
0
0
1
1
A14
Operation Mode
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] HIGH or through the configuration register
software sequence with DQ = 0001h on the third cycle.
Active LOW
Active HIGH (default)
Asserted one data cycle before delay (default)
Asserted during delay
A13
13 12 11
Counter
Latency
0
1
0
1
0
1
0
1
All burst WRITEs are continuous.
A12A11 A10
WAIT Polarity
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
WAIT Configuration
16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Latency Counter
Polarity
WAIT
10
Must be set to "0"
Reserved
9
A9
Configuration (WC)
WAIT
8
23
A8
BCR[6]
Must be set to "0"
0
1
Reserved
BCR[5]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
A7
0
1
Rising edge (default)
Not supported
BCR[3]
Configuration (CC)
1/4 Drive
0
1
Full Drive (default)
Output Impedance
Clock
Clock Configuration
BCR[2]
6
0
0
0
1
A6
Burst wraps within the burst length
Burst no wrap (default)
BCR[1] BCR[0]
0
1
1
1
Impedance
Configuration Registers
Output
Burst Wrap (Note 1)
5
A5
1
0
1
1
Must be set to "0"
©2005 Micron Technology, Inc. All rights reserved.
Reserved
4 words
8 words
16 words
Continuous burst (default)
A4
4
Burst Length (Note 1)
Wrap (BW)*
Burst
3
A3
Length (BL)*
2
A2 A1 A0
Burst
1
0