MT8LSDT3264HY-133D2 Micron Technology Inc, MT8LSDT3264HY-133D2 Datasheet

no-image

MT8LSDT3264HY-133D2

Manufacturer Part Number
MT8LSDT3264HY-133D2
Description
MODULE SDRAM 256MB 144SODIMM
Manufacturer
Micron Technology Inc
Series
-r
Datasheet

Specifications of MT8LSDT3264HY-133D2

Main Category
DRAM Module
Sub-category
SDRAM
Module Type
144SODIMM
Device Core Size
64b
Organization
32Mx64
Total Density
256MByte
Chip Density
256Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
548mA
Number Of Elements
8
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
144
Mounting
Socket
Memory Type
SDRAM
Memory Size
256MB
Speed
133MHz
Features
-
Package / Case
144-SODIMM
Lead Free Status / RoHS Status
Compliant
SMALL-OUTLINE
SDRAM MODULE
Features
• PC100- and PC133-compliant, 144-pin, small-
• Utilizes 125 MHz and 133 MHz SDRAM
• Unbuffered
• 64MB (8 Meg x 64), 128MB (16 Meg x 64), and
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can
• Internal SDRAM banks for hiding row access/
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode: Standard and Low Power
• 64MB and 128MB: 64ms, 4,096-cycle (15.625µs)
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
• Gold edge contacts
Table 1:
CL = CAS (READ) latency
Table 2:
09005aef8077d63a
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
MARKING
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
MODULE
outline, dual in-line memory module (SODIMM)
components
256MB (32 Meg x 64)
edge of system clock
be changed every clock cycle
precharge
refresh interval; 256MB: 64ms, 8,192-cycle
(7.8125µs) refresh interval
-13E
-133
-10E
FREQUENCY
133 MHz
133 MHz
100 MHz
CLOCK
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Timing Parameters
Address Table
CL = 2
ACCESS TIME
5.4ns
6ns
CL = 3
5.4ns
64Mb (4 Meg x16)
4 (BA0, BA1)
4K (A0–A11)
256 (A0–A7)
2 (S0#, S1#)
SETUP
TIME
1.5ns
1.5ns
64MB
2ns
4K
HOLD
TIME
0.8ns
0.8ns
1ns
1
NOTE:
MT8LSDT864(L)H(I) – 64MB
MT8LSDT1664(L)H(I) – 128MB
MT8LSDT3264(L)H(I) – 256MB
For the latest data sheet, please refer to the Micron
site:
Options
• Self Refresh Current
• Operating Temperature Range
• Package
• Memory Clock/CAS Latency
Standard 1.25in. (31.75mm)
64MB, 128MB, 256MB (x64, DR)
Figure 1: 144-Pin SODIMM (MO-190)
128Mb (8 Meg x 16)
Standard
Low-Power
Commercial (0 C to +70 C
Industrial (-40 C to +85 C)
144-pin SODIMM (standard)
144-pin SODIMM (lead-free)
7.5ns (133 MHz)/CL = 2
7.5ns (133 MHz)/CL = 3
10ns (100 MHz)/CL = 2
www.micron.com/products/modules
4 (BA0, BA1)
4K (A0–A11)
512 (A0–A8)
2 (S0#, S1#)
1. Contact Micron for product availability.
2. Low Power and Industrial Temperature options
128MB
4K
not available concurrently; Industrial Tempera-
ture option available in -133 speed only.
144-PIN SDRAM SODIMM
©2004 Micron Technology, Inc. All rights reserved.
)
256Mb (16 Meg x 16)
4 (BA0, BA1)
8K (A0–A12)
512 (A0–A8)
2 (S0#, S1#)
256MB
8K
Marking
None
None
-13E
-10E
L
-133
I
1, 2
Y
1, 2
G
1
®
Web

Related parts for MT8LSDT3264HY-133D2

MT8LSDT3264HY-133D2 Summary of contents

Page 1

... SMALL-OUTLINE SDRAM MODULE Features • PC100- and PC133-compliant, 144-pin, small- outline, dual in-line memory module (SODIMM) • Utilizes 125 MHz and 133 MHz SDRAM components • Unbuffered • 64MB (8 Meg x 64), 128MB (16 Meg x 64), and 256MB (32 Meg x 64) • Single +3.3V power supply • ...

Page 2

... The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT1664HG-133B1 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) 144-PIN SDRAM SODIMM MODULE DENSITY CONFIGURA-TION 64MB 8 Meg x 64 64MB 8 Meg x 64 ...

Page 3

... A2 69 S0# 105 S1# 107 SS NOTE: 1. Pin Connect for 64MB and128MB modules, or A12 for 256MB module. Figure 2: Pin Locations (144-Pin SODIMM) Front View U2 U3 PIN 1 (all odd pins) 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) Table 5: PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL ...

Page 4

... Not Connected: These pins should be left unconnected. DNU – Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. 4 144-PIN SDRAM SODIMM Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 5

... WE# A0-A11 (64MB/128MB) A0-A12 (256MB) BA0-1 NOTE: 1. All resistor values are 10 unless otherwise specified. 2. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/support/numbering.html. 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) Figure 3: Functional Block Diagram ...

Page 6

... EEPROM device (DIMM) occur via a standard I using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAM devices must be powered up and initialized in a predefined manner ...

Page 7

... The ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in Table 7, Burst Definition Table, on page 8. Figure 4: Mode Register Definition 64MB Module and Reserved* WB *Should program M11 and M10 = “0, 0” to ensure compatibility with future devices ...

Page 8

... For a burst length of one, A0–Ai select the unique col- umn to be accessed, and mode register bit M3 is ignored for 64MB modules for 128MB and 256MB modules 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) Figure 5: CAS Latency Diagram ...

Page 9

Test modes and reserved states should not be used, because unknown operation or incompatibility with future versions may result. Write Burst Mode When the burst length programmed via M0- M2 applies to both READ and WRITE bursts; ...

Page 10

Commands The Truth Table provides a quick reference of avail- able commands. This is followed by written descrip- tion of each command. For a more detailed des- Table 9: Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH ...

Page 11

... NOTE: a. Value calculated as one module rank in this operating condition, and all other module ranks in power-down mode. b. Value calculated reflects all module ranks in this operating condition. 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) tional sections of this specification is not implied ...

Page 12

... NOTE: a. Value calculated as one module bank in this operating condition, and all other module banks in power-down mode. b. Value calculated reflects all module banks in this operating condition. 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) ...

Page 13

... Input Capacitance: CK, CKE, S# Input Capacitance: DQMB Inuput/Output Capacitnance: DQ Table 15: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 31; notes appear on page 15 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters AC CHARACTERISTICS PARAMETER Access time from CLK (positive edge) ...

Page 14

Table 16: AC Functional Characteristics Notes 11, 31; notes appear on page 15 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup ...

Page 15

... RAS used in -13E speed grade mod- t ule SPDs is calculated from RC - possible through the module pin, not what each memory device contributes. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. t RP; clock( ...

Page 16

SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Fig- ure 6, Data Validity, and Figure 7, Definition ...

Page 17

Table 17: EEPROM Device Select code The most significant bit (b7) is sent first Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating modes MODE RW BIT Current Address Read Random Address Read Sequential Read ...

Page 18

Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...

Page 19

... Total Number of SPD Memory Bytes 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of Module Ranks 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels t 9 SDRAM Cycle Time, CK (CAS Latency = SDRAM Access from CLK, AC (CAS Latency = 3) 11 Module Configuration Type 12 Refresh Rate/Type 13 ...

Page 20

... Week of Manufacture in BCD 95-98 Module Serial Number 99-125 Manufacturer-specific Data (RSVD) 126 System Frequency 127 SDRAM Component & Clock Detail NOTE The value of RAS used for -13E modules is calculated from 09005aef8077d63a SD8C8_16_32x64HG.fm - Rev. C 6/04 EN 64MB, 128MB, 256MB (x64, DR) ENTRY (VERSION) 32MB, 64MB, or 128MB ...

Page 21

R (2X) U2 0.071 (1.80) (2X) 0.236 (6.00) 0.100 (2.55) 0.079 (2.00) PIN 1 0.13 (3.30) U9 PIN 144 NOTE: All dimensions in inches (millimeters); Data Sheet Designation Released (No Mark): This data sheet contains mini- mum and ...

Related keywords