MT36VDDF25672Y-40BF3 Micron Technology Inc, MT36VDDF25672Y-40BF3 Datasheet
MT36VDDF25672Y-40BF3
Specifications of MT36VDDF25672Y-40BF3
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MT36VDDF25672Y-40BF3 Summary of contents
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... MT36VDDF12872 – 1GB MT36VDDF25672 – 2GB For component data sheets, refer to Micron’s Web site: Features • 184-pin, registered dual in-line memory module (RDIMM) • Tall- and standard-height PCB options • Fast data transfer rates: PC2100, PC2700, or PC3200 • 1GB (128 Meg x 72) and 2GB (256 Meg x 72) • ...
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... RCD and RP for -335 modules show 18ns to align with industry specifications; 1GB 8K 8K (A0–A12) 4 (BA0, BA1) 256Mb (64 Meg (A0–A9, A11) 2 (S0#, S1#) 1 256Mb DDR SDRAM Module Configuration Bandwidth 1GB 128 Meg ...
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... MT36VDDF25672G-335__ MT36VDDF25672Y-335__ MT36VDDF25672G-262__ MT36VDDF25672G-26A__ MT36VDDF25672G-265__ MT36VDDF25672Y-265__ Notes: 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT36VDDF12872Y-335G3. ...
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Pin Assignments and Descriptions Table 5: Pin Assignments 184-Pin DDR RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ17 47 REF 2 DQ0 25 DQS2 DQ1 ...
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... Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V). Supply SPD EEPROM power supply: +2.3V to +3.6V. Supply SSTL_2 reference voltage (V Supply Ground. – No connect: These pins are not connected on the module. 5 Pin Assignments and Descriptions 2 C bus. /2). DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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Functional Block Diagrams Figure 4: Functional Block Diagram – Tall-Height Layout (1GB, 2GB) S1# S0# DQS0 DQ0 DQ1 DQ2 DQ3 DQS9 DQ4 DQ5 DQ6 DQ7 DQS1 DQ8 DQ9 DQ10 DQ11 DQS10 DQ12 DQ13 DQ14 DQ15 DQS8 CB0 CB1 CB2 CB3 ...
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Figure 5: Functional Block Diagram – Standard-Height Layout (1GB) S1# S0# DQS0 DQ0 DQ DQ1 DQ DQ2 DQ DQ3 DQ DQS9 DQ DQ4 DQ5 DQ DQ DQ6 DQ7 DQ DQS1 DQ8 DQ DQ9 DQ DQ10 DQ DQ DQ11 DQS10 DQ ...
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Figure 6: Functional Block Diagram – Standard-Height Layout (2GB) S1# S0# DQS0 DQ0 DQ1 DQ2 DQ3 DQS9 DQ4 DQ5 DQ6 DQ7 DQS1 DQ8 DQ9 DQ10 DQ11 DQS10 DQ12 DQ13 DQ14 DQ15 DQS8 CB0 CB1 CB2 CB3 DQS2 DQ16 DQ17 DQ18 ...
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... DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differ- ential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce control, command, address, and clock signals loading by isolating DRAM from the system controller ...
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... Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability ...
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... Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. ...
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... RC = inputs change only during active READ or WRITE commands Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are Value calculated reflects all module ranks in this operating condition. PDF: 09005aef80772fd2/Source: 09005aef8075ebf6 DDF36C128_256x72.fm - Rev. G 9/08 EN 1GB, 2GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM ...
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... Operating bank interleave read current: Four device bank interleaving reads ( with auto precharge; and control inputs change only during active READ or WRITE commands Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are Value calculated reflects all module ranks in this operating condition. PDF: 09005aef80772fd2/Source: 09005aef8075ebf6 DDF36C128_256x72 ...
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... (MIN); Address and control inputs change only during active READ or WRITE commands Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are Value calculated reflects all module ranks in this operating condition. PDF: 09005aef80772fd2/Source: 09005aef8075ebf6 DDF36C128_256x72.fm - Rev. G 9/08 EN ...
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... Timing and switching specifications for the register listed above are critical for proper oper- ation of the DDR SDRAM RDIMMs. These are meant subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. ...
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Table 13: PLL Specifications CVF857 device or equivalent JESD82-1A Parameter DC high-level input voltage DC low-level input voltage Input voltage (limits) Input differential-pair cross voltage Input differential voltage Input differential voltage Input current Dynamic supply current Dynamic supply current Dynamic ...
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Serial Presence-Detect Table 15: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current GND ...
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... TYP Back view U21 U22 U23 U24 U25 U32 U31 U33 U40 Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 Module Dimensions U8 U9 U10 U39 43.31 (1.705) 43.05 (1.695) U16 U17 U18 17.78 (0.7) TYP 10.0 (0.394) TYP 49 ...
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... TYP TYP 120.65 (4.75) TYP Back view U27 U25 U26 U28 U29 U30 U37 U36 U38 73.28 (2.88) TYP 19 Module Dimensions U9 U10 U11 U12 30.61 (1.205) 30.35 (1.195) U18 U20 17.78 (0.7) U19 TYP 10.0 (0.394) TYP 49.53 (1.95) Pin 92 TYP ...
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... U24 U25 U27 U28 U26 U34 U35 U37 U38 U36 73.28 (2.88) TYP ® their respective owners. characterization sometimes occur. 20 Module Dimensions U8 U9 U10 30.61 (1.205) 30.35 (1.195) U18 U20 U19 17.78 (0.7) TYP 10.0 (0.394) TYP 49.53 (1.95) Pin 92 TYP ...