HYS64D16301EU-5-C Infineon Technologies, HYS64D16301EU-5-C Datasheet
HYS64D16301EU-5-C
Specifications of HYS64D16301EU-5-C
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HYS64D16301EU-5-C Summary of contents
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HYS64D[16/32/64][300/301/320][G/H]U–5–C HYS72D[32/64][300/301/320][G/H]U–5–C HYS64D[16/32/64][300/301/320][G/H]U–6–C HYS72D[32/64][300/301/320][G/H]U–6–C 184-Pin Unbuffered Double Data Rate SDRAM UDIMM DDR SDRAM ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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HYS64D[16/32/64][300/301/320][G/H]U–5–C HYS72D[32/64][300/301/320][G/H]U–5–C HYS64D[16/32/64][300/301/320][G/H]U–6–C HYS72D[32/64][300/301/320][G/H]U–6– ...
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HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C, HYS64D[16/32/64][300/301/320][G/H]U–6–C Revision History: Rev. 1.02 Previous Version: Rev. 1.01 12 editorial change We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 5 Rev. 1.01, 2004-07 ...
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... Gold plated contacts • DDR400 Speed Grade supported Table 1 Performance Part Number Speed Code Module Speed Grade Component Module max. Clock Frequency 1.2 Description The HYS64D[16/32/64][300/301/320][G/H]U–5–C, HYS72D[32/64][300/301/320][G/H]U–5–C, HYS64D[16/32/64][300/301/320][G/H]U–6–C and HYS72D[32/64][300/301/320][G/H]U–6–C are industry standard 184-Pin Unbuffered Double Data Rate SDRAM (UDIMM) organized as 16M × ...
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... Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module ...
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... Address Signal 12 Note: Module based on 256 Mbit or larger dies NC – Note: 128 Mbit module I SSTL Address Signal 13 Note: 1 Gbit module NC – Note: Module based on 512 Mbit smaller dies I/O SSTL Data Bus 63:0 I/O SSTL I/O SSTL I/O SSTL I/O SSTL I/O ...
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... Note: ECC type module – Note: Non-ECC module SSTL Check Bit 4 Note: ECC type module – Note: Non-ECC module SSTL Check Bit 5 Note: ECC type module – Note: Non-ECC module SSTL Check Bit 6 Note: ECC type module – Note: Non-ECC module SSTL Check Bit 7 Note: ECC type module – ...
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... SSTL 159 DM5 I SSTL 169 DM6 I SSTL 177 DM7 I SSTL 140 DM8 I SSTL Data Mask 8 Note: ECC type module NC NC – Note: Non-ECC module EEPROM 92 SCL I CMOS Serial Bus Clock 91 SDA I/O OD Serial Bus Data 181 SA0 I CMOS Slave Address Select ...
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... Pin 086 Pin 088 - - Pin 090 - Pin 092 11 Unbuffered DDR SDRAM Modules Pin Configuration Abbreviations for Buffer Type Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR ...
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... I/O12 DQ5 I/O13 DQ6 I/O14 DQ7 I/O15 Block Diagram Raw Card C (×64, 1 Rank, ×16) Figure 2 Notes Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules SDRAMs # row/bank/ SDRAMs columns bits 16M ×16 4 13/2/9 32M ×8 8 13/2/10 32M ×8 ...
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... DQ44 I/O 4 DQ45 I/O 5 DQ46 I/O 6 DQ47 I/O 7 Ω ± Table Ω ± Clock Input CK0, CK0 CK1, CK1 CK2, CK2 13 Unbuffered DDR SDRAM Modules Pin Configuration Clock Signal Loads Number of SDRAMs NC 2 SDRAMs 2 SDRAMs V : SPD EEPROM SDRAMs DDQ DD DDQ SDRAMs ...
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... SCL SCL SAD SAD SA0 A0 SA1 A1 SA2 Table 10 Ω ± Clock Input 5 % Ω ± CK0, CK0 CK1, CK1 CK2, CK2 14 Unbuffered DDR SDRAM Modules Pin Configuration V : SPD EEPROM SDRAMs DDQ V : SDRAMs REF V : SDRAMs Strap: see Note 1 D3 DM6 DM DQS6 DQS DQ48 ...
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... DQ62 I/O 7 DQ63 SCL SAD SA0 SA1 SA2 Table 11 Ω ± Clock Input 5 % Ω ± CK0, CK0 CK1, CK1 CK2, CK2 15 Unbuffered DDR SDRAM Modules Pin Configuration V : SPD EEPROM SDRAMs D0 - D15 DD DDQ V : SDRAMs D0 - D15 REF V : SDRAMs D0 - D15 SS Strap: see Note 1 D4 ...
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... DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM8/DQS17 : SDRAMs D0 - D17 Table 12 Ω ± Clock Input 5 % Ω ± CK0, CK0 CK1, CK1 CK2, CK2 16 Unbuffered DDR SDRAM Modules Pin Configuration SCL SCL SAD SAD SA0 A0 SA1 A1 SA2 DQS4 DQS DQS ...
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... V V DDQ DDQ DDQ DDQ – – 0.04 REF 0.15 REF V –0.3 V –0.3 0. Unbuffered DDR SDRAM Modules Electrical Characteristics Values Unit Note/ Test Typ. Max. V – +0.5 V DDQ – +3.6 V – +3.6 V – +3.6 V °C – +70 °C – +150 1 – – ...
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... REF (DC) REF system supply for signal termination resistors, is expected to be set equal REF V stabilizes. REF 19 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit Note/Test Condition 7) — µA Any input 0 V ≤ All other pins not under test 8) µA DQs are disabled ≤ ...
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... DQ, DQS and DM; IH,MIN IN REF or ≤ IH,MIN IL,MAX for DQ, DQS and DM. ILMAX IN REF IH,MIN RC RAS,MAX OUT 20 Unbuffered DDR SDRAM Modules Electrical Characteristics = V for DQ, DQS and DM. REF Rev. 1.01, 2004-07 Symbol I DD0 I DD1 I DD2P I DD2F I DD2Q I DD3P I DD3N I DD4R I DD4W I DD5 I DD6 I DD7 ...
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... 2 ° values of the component data sheet as follows: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules data sheet values as × I DDx 21 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit 512MB ×72 2 Ranks –5 Max ...
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... DQ loading 2 ° values of the component data sheet as follows: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules data sheet values as × I DDx 22 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit 512MB ×72 2 Ranks – ...
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... DSH t 0.2 — DSS min — — +0 0.6 — IH 0.7 — t 2.2 — IPW 23 Unbuffered DDR SDRAM Modules Electrical Characteristics –6 Unit Note/ Test Condition DDR333 Min. Max. 2)3)4)5) –0.7 +0.7 ns 2)3)4)5) t 0.45 0. 3.0 2)3)4) 2.5 2)3)4)5) 7 2.0 2)3)4)5) ...
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... XSNR t 200 — XSRD = +2.5 V ± 0.2 V (DDR333 CK/CK slew rate are ≥ 1.0 V/ns. V REF V stabilizes. REF 24 Unbuffered DDR SDRAM Modules Electrical Characteristics –6 Unit Note/ Test Condition DDR333 Min. Max. 0.75 — ns fast slew rate 3)4)5)6)9) 0.8 — ns ...
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... The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C . IL(ac) 25 Unbuffered DDR SDRAM Modules Electrical Characteristics t is equal to the actual system clock ...
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... Component Attributes CLmax -0.5 (Byte 18) [ns SDRAM @ CLmax -0.5 [ns CLmax -1 (Byte 18) [ns] CK Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks PC3200U– PC3200U– PC3200U– 30330 30330 30330 Rev 0 ...
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... Table 19 SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–5–C Label Code Jedec SPD Revision Byte# Description t 26 SDRAM @ CLmax -1 [ns [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank [ns [ns [ns [ns not used t 41 [ns] RCmin t 42 [ns] RFCmin t 43 [ns] CKmax t 44 ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( 127 Blank Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 × ...
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... CLmax -0.5 (Byte 18) [ns SDRAM @ CLmax -0.5 [ns CLmax -1 (Byte 18) [ns SDRAM @ CLmax -1 [ns] AC Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks PC3200U– PC3200U– PC3200U– 30330 30330 30330 Rev 0 ...
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... Table 20 SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–5–C Label Code Jedec SPD Revision Byte# Description t 27 [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank [ns [ns [ns [ns not used t 41 [ns] RCmin t 42 [ns] RFCmin t 43 [ns] CKmax 44 t [ns] DQSQmax t 45 [ns] ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( 127 Blank Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 × ...
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... CLmax -0.5 (Byte 18) [ns SDRAM @ CLmax -0.5 [ns CLmax -1 (Byte 18) [ns SDRAM @ CLmax -1 [ns] AC Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks PC2700U– PC2700U– PC2700U– 25330 25330 25330 Rev 0 ...
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... Table 21 SPD Codes for HYS[64/72]D[16/32/64][300/301/320]HU–6–C Label Code Jedec SPD Revision Byte# Description t 27 [ns] RPmin t 28 [ns] RRDmin 29 t [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank [ns [ns [ns [ns not used 41 t [ns] RCmin t 42 [ns] RFCmin 43 t [ns] CKmax t 44 [ns] DQSQmax t 45 [ns] ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( -127 Blank Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 × ...
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... CLmax -0.5 (Byte 18) [ns SDRAM @ CLmax -0.5 [ns CLmax -1 (Byte 18) [ns SDRAM @ CLmax -1 [ns] AC Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 ×64 1 Rank 1 Rank 2 Ranks PC2700U– PC2700U– PC2700U– 25330 25330 25330 Rev 0 ...
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... Table 22 SPD Codes for HYS[64/72]D[16/32/64][300/301/320]GU–6–C Label Code Jedec SPD Revision Byte# Description t 27 [ns] RPmin t 28 [ns] RRDmin t 29 [ns] RCDmin t 30 [ns] RASmin 31 Module Density per Rank [ns [ns [ns [ns not used t 41 [ns] RCmin t 42 [ns] RFCmin t 43 [ns] CKmax t 44 [ns] DQSQmax t 45 [ns] ...
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... Part Number, Char 18 91 Module Revision Code 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week Module Serial Number ( -127 Blank Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C Unbuffered DDR SDRAM Modules 128 MB 256 MB 512 MB ×64 ×64 × ...
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... Package Outlines 1 2.36 ±0.1 ø0 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 7 Package Outlines - Raw Card C 128 MByte, 1 Rank Module Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ± ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 8 Package Outline - Raw Card A 256 MByte, 1 Rank Module Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C 133.35 128.95 A 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0.1 0 Unbuffered DDR SDRAM Modules ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 9 Package Outline - Raw Card A 256 MByte, 1 Rank ECC Module Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ± ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 10 Package Outline - Raw Card B 512 MByte, 2 Ranks Module Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C 133.35 128.95 A 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 Unbuffered DDR SDRAM Modules ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 11 Package Outline - Raw Card B 512 MByte, 2 Ranks ECC Module Data Sheet HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 ...
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... Published by Infineon Technologies AG ...