MT36HTF51272PY-80EE1

... MT36HTF25672(P) – 2GB MT36HTF51272(P) – 4GB For the latest component data sheets, refer to Micron’s Web site: Features • 240-pin, registered dual in-line memory module • Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400 • 2GB (256 Meg x 72), 4GB (512 Meg x 72) • ...

... Table 2: Addressing Refresh count Row address Device bank address Device page size per bank Device configuration Column address Module rank address Table 3: Part Numbers and Timing Parameters – 2GB Modules Base device: MT47H128M4 Module 1 Part Number Density MT36HTF25672(P)Y-80E__ MT36HTF25672(P)Y-800__ MT36HTF25672(P)Y-667__ MT36HTF25672(P)Y-53E__ ...

Pin Assignments and Descriptions Table 5: Pin Assignments 240-Pin RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ19 61 REF DQ0 33 DQ24 63 4 DQ1 34 ...

... Data input/output: Bidirectional data bus. (SSTL_18) CB0–CB7 I/O Check bits. (SSTL_18) SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module Output Parity error found on the address and control bus (open drain) ...

Functional Block Diagrams Figure 2: Functional Block Diagram – 2GB V SS RS0# RS1# DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS8 DQS8# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 DQS7# Rank 0 = U1–U5, U8–U16, U18–U21 Rank 1 ...

Figure 3: Functional Block Diagram – 4GB V SS RS0# RS1# Rank 0 = U1–U5, U8–U16, U18–U21 Rank 1 = U22–U25, U27–U40 S0# S1# BA0–BA1 A0–A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 PAR_IN RESET# PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb HTF36C256_512x72.fm - ...

... DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer ...

... Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’ ...

... DD HIGH HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes: 1. Value calculated as one module rank in this operating condition, all other module ranks Value calculated reflects all module ranks in this operating condition. PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb HTF36C256_512x72 ...

... DD HIGH HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching Notes: 1. Value calculated as one module rank in this operating condition, all other module ranks Value calculated reflects all module ranks in this operating condition. PDF: 09005aef818e3fc8/Source: 09005aef818e3fdb HTF36C256_512x72 ...

... Timing and switching specifications for the register listed above are critical for proper oper- ation of the DDR2 SDRAM registered DIMMs. These are meant subset of the param- eters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. ...

Table 12: PLL Specifications CU877 device or equivalent JESD82-8.01 Parameter Symbol DC high-level input voltage V DC low-level input voltage V Input voltage (limits high-level input voltage V DC low-level input voltage V Input differential-pair cross V voltage ...

Serial Presence-Detect Table 14: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input ...

... Number of SPD bytes used by Micron 1 Total number of bytes in SPD device 2 Fundamental memory type 3 Number of row addresses on SDRAM 4 Number of column addresses on SDRAM 5 DIMM height and module ranks 6 Module data width 7 Reserved 8 Module voltage interface levels t 9 SDRAM cycle time, CK (CL = MAX value, see byte 18) ...

... SDRAM access from CK, 27 MIN row precharge time, 28 MIN row active-to-row active, 29 MIN RAS#-to-CAS# delay, 30 MIN active-to-precharge time, 31 Module rank density 32 Address and command setup time, 33 Address and command hold time, 34 Data/data mask input setup time, 35 Data/data mask input hold time, t ...

... SPD revision 63 Checksum for bytes 0–62 ECC/ECC and Parity 64 Manufacturer’s JEDEC ID code 65–71 Manufacturer’s JEDEC ID code 72 Manufacturing location 73–90 Module part number (ASCII) 91 PCB identification code 92 Identification code (continued) 93 Year of manufacture in BCD 94 Week of manufacture in BCD 95–98 Module serial number 99– ...

... U36 U38 U39 U35 U40 U37 5.0 (0.197) TYP 63.0 (2.48) TYP Micron Technology, Inc., reserves the right to change products or specifications without notice. 17 Module Dimensions U10 U11 30.50 (1.20) 29.85 (1.175) U20 U21 17.78 (0.70) TYP 10.0 (0.394) TYP PIN 120 ...

... U35 U36 U37 U38 5.0 (0.197) TYP 63.0 (2.48) TYP ® their respective owners. Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 Module Dimensions U10 U11 30.50 (1.20) 29.85 (1.175) U20 U21 17.78 (0.70) TYP 10.0 (0.394) TYP ...