MT18VDDF12872G40BC3 Micron Technology Inc, MT18VDDF12872G40BC3 Datasheet
MT18VDDF12872G40BC3
Specifications of MT18VDDF12872G40BC3
Related parts for MT18VDDF12872G40BC3
MT18VDDF12872G40BC3 Summary of contents
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... MT18VDDF6472D – 512MB MT18VDDF12872D – 1GB For component data sheets, refer to Micron’s Web site: Features • 184-pin, registered dual in-line memory module (RDIMM) • Fast data transfer rates: PC2100, PC2700, or PC3200 • 512MB (64 Meg x 72) and 1GB (128 Meg x 72) • ...
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... RCD and RP for -335 modules show 18ns to align with industry specifications; 512MB 8K 8K (A0–A12) 4 (BA0, BA1) 256Mb (32 Meg (A0–A9) 2 (S0#, S1#) 1 256Mb DDR SDRAM Module Configuration Bandwidth 64 Meg ...
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... Table 4: Part Numbers and Timing Parameters – 1GB Modules Base device: MT46V64M8, Module 2 Part Number Density MT18VDDF12872DG-40B__ MT18VDDF12872DY-40B__ MT18VDDF12872DG-335__ MT18VDDF12872DY-335__ MT18VDDF12872DY-262__ MT18VDDF12872DG-26A__ MT18VDDF12872DG-265__ Notes: 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions ...
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... Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V). Supply Serial EEPROM power supply: +2.3V to +3.6V. Supply SSTL_2 reference voltage (V Supply Ground. – No connect: These pins are not connected on the module. 4 Pin Assignments and Descriptions 2 C bus. /2). DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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Functional Block Diagrams Figure 3: Functional Block Diagram R/C H (-40B) RS1# RS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 ...
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Figure 4: Functional Block Diagram R/C B (-335, -262, -26A, -265) RS1# RS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 ...
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... DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differ- ential clock signals (CK, CK#) to the DDR SDRAM devices. The register(s) and PLL reduce control, command, address, and clock signals loading by isolating DRAM from the system controller ...
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... Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability ...
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... Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. ...
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... RC = control inputs change only during active READ or WRITE commands Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are Value calculated reflects all module ranks in this operating condition. PDF: 09005aef807eb17d/Source: 09005aef807d24c9 ddf18c64_128x72d.fm - Rev. D 10/08 EN ...
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... Address and control inputs change only during active READ or WRITE commands Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are Value calculated reflects all module ranks in this operating condition. PDF: 09005aef807eb17d/Source: 09005aef807d24c9 ddf18c64_128x72d ...
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... (MIN); Address and control inputs change only during active READ or WRITE commands Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks are Value calculated reflects all module ranks in this operating condition. PDF: 09005aef807eb17d/Source: 09005aef807d24c9 ddf18c64_128x72d.fm - Rev. D 10/08 EN ...
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... Timing and switching specifications for the register listed above are critical for proper oper- ation of the DDR SDRAM RDIMM devices. These are meant subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. ...
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Table 13: PLL Specifications CVF857 device or equivalent JESD82-1A Parameter DC high-level input voltage DC low-level input voltage Input voltage (limits) Input differential-pair cross voltage Input differential voltage Input differential voltage Input current Dynamic supply current Dynamic supply current Dynamic ...
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Serial Presence-Detect Table 15: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current GND ...
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... TYP TYP TYP 64.77 (2.55) TYP 120.65 (4.75) TYP Back view U19 U17 U18 U20 U21 73.28 (2.88) 16 Module Dimensions U12 U9 U10 U11 17.78 (0.70) TYP 10.0 (0.394) TYP 49.53 (1.95) Pin 92 TYP U22 U23 U24 3.8 (0.15) TYP ...
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... TYP TYP 64.77 (2.55) TYP 120.65 (4.75) TYP Back view U17 U14 U15 U18 U19 U16 73.28 (2.88) tive owners. 17 Module Dimensions U9 U10 U11 28.73 (1.131) 28.42 (1.119) 17.78 (0.70) TYP 10.0 (0.394) TYP 49.53 (1.95) Pin 92 TYP U20 U21 U22 3 ...