MT18VDDF12872G40BC3 Micron Technology Inc, MT18VDDF12872G40BC3 Datasheet - Page 10

• Manufacturer Part Number: MT18VDDF12872G40BC3
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872G40BC3

• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Not Compliant

I
Table 9:
PDF: 09005aef807eb17d/Source: 09005aef807d24c9
ddf18c64_128x72d.fm - Rev. D 10/08 EN
Parameter/Condition
Operating one bank active-precharge current:
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
I
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge;
control inputs change only during active READ or WRITE commands
DD
OUT
CK =
RC =
CK =
IN
= V
Specifications
= 0mA
t
t
t
CK (MIN); I
RAS (MAX);
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
REF
t
t
CK =
CK =
for DQ, DM, and DQS
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
I
Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
DD
OUT
Specifications and Conditions – 512MB (Die Revision K)
t
Notes:
CK =
= 0mA; Address and control inputs changing once per clock
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
t
RC =
in I
DD
t
RC (MIN);
2P (CKE LOW) mode.
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
t
CK =
t
RC =
t
CK (MIN); Address and
t
RC (MIN);
t
CK =
t
t
RFC =
RFC = 7.8125µs
10
t
t
CK (MIN);
RC =
t
t
CK =
RFC (MIN)
t
CK =
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC (MIN);
t
CK (MIN);
t
CK
;
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
Electrical Specifications
1
1
2
2
1
2
2
2
1
2
2
1
©2004 Micron Technology, Inc. All rights reserved
1,116
1,080
1,656
1,656
2,880
2,646
-40B
936
900
630
108
72
72
1,071
1,476
1,476
2,880
2,466
-335
846
900
540
990
108
72
72
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA